JPS54159832A - Adder and subtractor for numbers different in data length - Google Patents

Adder and subtractor for numbers different in data length

Info

Publication number
JPS54159832A
JPS54159832A JP6870278A JP6870278A JPS54159832A JP S54159832 A JPS54159832 A JP S54159832A JP 6870278 A JP6870278 A JP 6870278A JP 6870278 A JP6870278 A JP 6870278A JP S54159832 A JPS54159832 A JP S54159832A
Authority
JP
Japan
Prior art keywords
data
adder
length
data length
subtractor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6870278A
Other languages
Japanese (ja)
Inventor
Yasuhiro Nara
Isao Aizawa
Takashi Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6870278A priority Critical patent/JPS54159832A/en
Publication of JPS54159832A publication Critical patent/JPS54159832A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/3816—Accepting numbers of variable word length

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To perform addition and subtraction of numbers different in data length by an adder, an incrementer, and 1's complement circuits, which are provided in the input part for data having a longer data length and the output part to obtain the calculation result, in case of addition and subtraction of numbers different in data length. CONSTITUTION:In the adder and subtractor which calculates two data, at least, different in bit length, and adder 3 having a bit width corresponding to the bit length of short data B, and incrementer 4 having a width corresponding to the difference of bit length between two data are provided. Then, 1's complement circuits 6 and 7 are provided in the input part of data A having a longer data length and respective output parts of adder 3 and incrementer 4, and 1's complement circuits 6 and 7 are made available only at a subtraction time.
JP6870278A 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length Pending JPS54159832A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6870278A JPS54159832A (en) 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6870278A JPS54159832A (en) 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length

Publications (1)

Publication Number Publication Date
JPS54159832A true JPS54159832A (en) 1979-12-18

Family

ID=13381353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6870278A Pending JPS54159832A (en) 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length

Country Status (1)

Country Link
JP (1) JPS54159832A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57186561A (en) * 1981-05-04 1982-11-17 Rite Hite Corp Locking device which is freely released
JPH03255525A (en) * 1990-03-05 1991-11-14 Fujitsu Ltd Three-input adding circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57186561A (en) * 1981-05-04 1982-11-17 Rite Hite Corp Locking device which is freely released
JPH027853B2 (en) * 1981-05-04 1990-02-21 Abon Corp
JPH03255525A (en) * 1990-03-05 1991-11-14 Fujitsu Ltd Three-input adding circuit

Similar Documents

Publication Publication Date Title
JPS54159831A (en) Adder and subtractor for numbers different in data length using counter circuit
JPS54159832A (en) Adder and subtractor for numbers different in data length
JPS55123701A (en) Command generation system
JPS5378742A (en) Multiplication control system
JPS57199044A (en) Multiplying device
JPS5291626A (en) Input data correction system in electronic apparatus
JPS51124342A (en) Information processing unit
GB1531470A (en) Circuit arrangement for adding and subtracting
JPS5378743A (en) Multiplier
JPS54112134A (en) Logical operation circuit
JPS5556271A (en) Calculator
JPS529337A (en) Small electronic computer
JPS55164942A (en) Division circuit
JPS5315032A (en) Fraction arismetic control unit
JPS54162936A (en) Data processor
JPS5298443A (en) Small computer
JPS57189249A (en) Operating circuit
JPS53103335A (en) Logic arithmetic circuit
JPS5422140A (en) Digital differential analyzer
JPS5336152A (en) Arithmetic circuit
JPS576976A (en) Bar width detecting system
JPS5347243A (en) Logarithmic arithmetic unit
JPS5591027A (en) Information processor
JPS5248435A (en) Key input unit
JPS5442938A (en) Directional difference arithmetic circuit