JPS53103335A - Logic arithmetic circuit - Google Patents

Logic arithmetic circuit

Info

Publication number
JPS53103335A
JPS53103335A JP1829977A JP1829977A JPS53103335A JP S53103335 A JPS53103335 A JP S53103335A JP 1829977 A JP1829977 A JP 1829977A JP 1829977 A JP1829977 A JP 1829977A JP S53103335 A JPS53103335 A JP S53103335A
Authority
JP
Japan
Prior art keywords
arithmetic circuit
logic arithmetic
carry
case
ratching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1829977A
Other languages
Japanese (ja)
Other versions
JPS5537029B2 (en
Inventor
Kazuo Murano
Toshitaka Tsuda
Shigeyuki Umigami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1829977A priority Critical patent/JPS53103335A/en
Publication of JPS53103335A publication Critical patent/JPS53103335A/en
Publication of JPS5537029B2 publication Critical patent/JPS5537029B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE: To increase the operation speed, by adding the partial product immediately to the preceding operation result in the case of the cumulative integration and ratching once the carry to have an addition including the carry in the next operation in the case of the subtraction mode.
COPYRIGHT: (C)1978,JPO&Japio
JP1829977A 1977-02-21 1977-02-21 Logic arithmetic circuit Granted JPS53103335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1829977A JPS53103335A (en) 1977-02-21 1977-02-21 Logic arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1829977A JPS53103335A (en) 1977-02-21 1977-02-21 Logic arithmetic circuit

Publications (2)

Publication Number Publication Date
JPS53103335A true JPS53103335A (en) 1978-09-08
JPS5537029B2 JPS5537029B2 (en) 1980-09-25

Family

ID=11967723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1829977A Granted JPS53103335A (en) 1977-02-21 1977-02-21 Logic arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS53103335A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713491A (en) * 1980-03-19 1982-01-23 Casio Computer Co Ltd Overflow processor for digital filter
JPS62187933A (en) * 1987-02-06 1987-08-17 Hitachi Ltd Adder/subtractor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713491A (en) * 1980-03-19 1982-01-23 Casio Computer Co Ltd Overflow processor for digital filter
JPS62187933A (en) * 1987-02-06 1987-08-17 Hitachi Ltd Adder/subtractor
JPH0353650B2 (en) * 1987-02-06 1991-08-15 Hitachi Seisakusho Kk

Also Published As

Publication number Publication date
JPS5537029B2 (en) 1980-09-25

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