JPS54159833A - Decimal multiplier - Google Patents

Decimal multiplier

Info

Publication number
JPS54159833A
JPS54159833A JP6910378A JP6910378A JPS54159833A JP S54159833 A JPS54159833 A JP S54159833A JP 6910378 A JP6910378 A JP 6910378A JP 6910378 A JP6910378 A JP 6910378A JP S54159833 A JPS54159833 A JP S54159833A
Authority
JP
Japan
Prior art keywords
multiplier
digit
register
contents
repeated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6910378A
Other languages
Japanese (ja)
Other versions
JPS5626865B2 (en
Inventor
Minoru Nishisaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6910378A priority Critical patent/JPS54159833A/en
Publication of JPS54159833A publication Critical patent/JPS54159833A/en
Publication of JPS5626865B2 publication Critical patent/JPS5626865B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4915—Multiplying; Dividing

Abstract

PURPOSE:To shorten the processing time by inspecting the number of significant digits of a multiplier to control data bus switches so that multiplier additions may be repeated by the number of significant digits when one multiplier addition is performed in an adder circuit in plural times. CONSTITUTION:Accumulation of multiplier values is started under the control of arithmetic control circuit 7. In one accumulation operation, data bus switches 11 and 12 are turned on and off respectively first, and contents of lower-digit arithmetic work register 4 and lower-digit multiplier storage register 2 are added in adder circuit 6, and the result is stored in register 4. Next, switches 11 and 12 are switched turning-off and on respectively, and contents of upper-digit multiplier storage register 1 and upper-digit arithmetic work register 3 are added in circuit 6. At this time, contents of carry register 9 are added together with them, and the result is stored in register 3. This operation is repeated to complete the multiplication between one lower digit of the multiplicand and the multiplier, and is repeated from the lowest digit in order by the number of significant digits of the multiplier.
JP6910378A 1978-06-08 1978-06-08 Decimal multiplier Granted JPS54159833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6910378A JPS54159833A (en) 1978-06-08 1978-06-08 Decimal multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6910378A JPS54159833A (en) 1978-06-08 1978-06-08 Decimal multiplier

Publications (2)

Publication Number Publication Date
JPS54159833A true JPS54159833A (en) 1979-12-18
JPS5626865B2 JPS5626865B2 (en) 1981-06-22

Family

ID=13392943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6910378A Granted JPS54159833A (en) 1978-06-08 1978-06-08 Decimal multiplier

Country Status (1)

Country Link
JP (1) JPS54159833A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3302885A1 (en) * 1982-01-29 1983-08-18 Hitachi, Ltd., Tokyo METHOD AND DEVICE FOR MULTIPLICATION
US4745569A (en) * 1983-12-28 1988-05-17 Hitachi, Ltd. Decimal multiplier device and method therefor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS636670U (en) * 1986-06-30 1988-01-18

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5175351A (en) * 1974-12-25 1976-06-29 Fujitsu Ltd Kosoku 10 shinjozanseigyohoshiki

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5175351A (en) * 1974-12-25 1976-06-29 Fujitsu Ltd Kosoku 10 shinjozanseigyohoshiki

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3302885A1 (en) * 1982-01-29 1983-08-18 Hitachi, Ltd., Tokyo METHOD AND DEVICE FOR MULTIPLICATION
US4745569A (en) * 1983-12-28 1988-05-17 Hitachi, Ltd. Decimal multiplier device and method therefor

Also Published As

Publication number Publication date
JPS5626865B2 (en) 1981-06-22

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