JPH0797312B2 - Arithmetic unit - Google Patents

Description

The present invention relates to an arithmetic unit for performing fixed point arithmetic.

(Prior Art) Conventionally, in the calculation of a fixed-point number, overflow is detected after the calculation result is determined.

FIG. 3 shows a conventional example of the above-mentioned arithmetic unit.
The conventional device has a first operand storage register 21, an inverter 2
2, selection circuit 23, second operand storage register 24, operation instruction storage flip-flop 25, calculator input "1" calculator 26, carry input "0" calculator 27, selection circuit 28, calculation result storage register 29, overflow It is composed of a detection circuit 30 and an overflow detection result storage flip-flop 31.

In the figure, when "1" for instructing subtraction is input as the operation instruction signal 100 ', this is set in the operation instruction storing flip-flop 25 and the selection circuit 23 selects the inverted output 2001' of the second operand B, and its complement. Is stored in the second operand storage register 24. When "0" indicating addition is input, it is also set in the operation instruction storing flip-flop 25, and the selection circuit 23 selects the output 2000 'of the second operand B, and B is stored in the second operand storage register 24. The computing unit 26 is a computing unit when there is a carrier, that is, when it is "1", and the computing unit 27 is a computing unit when there is no carrier, that is, when it is "0". The arithmetic units 26 and 27 perform arithmetic operations on the operands A and B, and their outputs are selected by the selection circuit 28. In the case of subtraction, the output of the operation instruction storing flip-flop 25 is "1", so the output result of the calculator 26 when there is a carrier is "0" in the case of addition, so the calculator 27 when there is no carrier
The output result of is stored in the calculation result storage register 29. The overflow detection circuit 30 detects an operation result stored in the operation result storage register 29 or an overflow, and stores the result in an overflow detection flip-flop.

(Problems to be Solved by the Invention) In the conventional device, overflow detection is performed after the calculation result is uniquely determined. That is, the overflow detection circuit 30 detects whether an overflow has occurred, and stores the result in the overflow detection result storage flip-flop 31. Therefore, there is a drawback that it takes a long time to detect the overflow.

It is an object of the present invention to provide a calculation result that does not require much time for overflow detection as in the past.

(Means for Solving the Problems) In order to achieve the above-mentioned object, in the arithmetic unit according to the present invention, the first arithmetic unit performs an operation when there is a carry input from the lower digit, and the second arithmetic unit carries out a carry input. In the fixed-point arithmetic unit, a calculation is performed when there is no value, the output result of the first or second arithmetic unit is selected by the selection instruction signal, and the output result is stored in the arithmetic result storage register.
A first overflow detection circuit that detects an overflow from the output result of the first arithmetic unit, and a second overflow detection circuit that detects an overflow from the output result of the second arithmetic unit When the output result of the first arithmetic unit is selected by the overflow detection circuit and the selection instruction signal, the output of the first overflow detection circuit is selected, and the output result of the second arithmetic unit is changed by the selection instruction signal. A selection circuit for selecting the output of the second overflow detection circuit when selected and an overflow detection result storage flip-flop for storing the output of the selection circuit are provided.

(Operation) According to the above configuration, the time required for overflow detection can be shortened, and the object of the present invention can be achieved completely.

(Example) Next, this invention is demonstrated in detail with reference to drawings. FIG. 1 is a block diagram showing an embodiment of an arithmetic unit according to the present invention.

In this embodiment, the first operand storage register 1, the inverter 2,
Selector circuit 3, second operand storage register 4, operation instruction storage flip-flop 5, operator 6 with carry input "1", operator 7 with carry input "0", select circuits 8 and 12, overflow detection circuits 10 and 11, It includes a calculation result storage register 9 and an overflow detection result storage flip-flop 13.

In this embodiment, the operation of the first operand, which is a fixed-point number, and the second operand, which is a fixed-point number, is performed as follows.

The first operand A is stored in the first operand storage register 1. On the other hand, the second operand B is the operation instruction signal 10
When 0 is “0” which indicates addition, the selection circuit 3 selects the value as it is, and when the operation instruction signal 100 is “1” which indicates subtraction, the inverter 2 uses “1”, “ A value obtained by inverting 0 ", that is, a complement of B is selected and stored in the second operand storage register 4.

A and B stored in the register 1 and the register 4 are added by the arithmetic unit 6 and the arithmetic unit 7.

The arithmetic unit 6 performs addition when there is a carry to the minimum digit (carry input “1”), that is, A + B + 1 for addition and A +++ 1 for subtraction.

On the other hand, the calculator 7 side adds A + when there is no carry to the smallest digit (carry input “0”), that is, when adding.
B, A + is added for subtraction.

The output 6000 which gives A + B + 1 or A +++ 1 calculated by the calculator 6 and the output 7000 which gives A + B or A + calculated by the calculator 7 are guided to the input of the selector 8 and the output 6000 of the calculator 6 becomes A + B + 1 or A ++.
1 is output to the overflow detection circuit 10 for detecting whether or not 1 is overflowing.
It is led to an overflow detection circuit 11 which detects whether + B or A + is overflowing. The outputs of these overflow detection circuits 10 and 11 are guided to the selector 12 which selects by the operation instruction signal 5000.

Operation instruction storage flip-flop 5 "0" when adding
However, when subtraction, "1" is stored.

When the addition is performed, the second operand B is stored as it is in the second operand storage register 4 as described above, and the result obtained by the operation unit 7 performing the operation of A + B is signal line 7000.
Is output to the signal line, and the overflow detection circuit 11 detects whether or not an overflow has occurred, and outputs "1" if an overflow has occurred and "0" if no overflow has occurred.
Output to 11000. At this time, the calculation instruction signal 100 indicates "0" which is addition, the output 5000 of the operation instruction storing flip-flop 5 also indicates "0" which is addition, and the selection circuit 8 indicates the signal line.
The selection circuit 12 selects the signal line 11000 and stores it in the operation result storage register 9 and the overflow detection result storage flip-flop 13, respectively.

When performing subtraction, the complement of the second operand B is stored in the second operand storage register 4 as described above. The result obtained by the arithmetic unit 6 performing the above-mentioned calculation of A ++ 1 is a signal line.
Output to 6000, and the overflow detection circuit 10 detects whether or not an overflow has occurred, and outputs "1" if an overflow has occurred and a "0" signal line if no overflow has occurred.
Output to 10000. At this time, the calculation instruction signal 100 indicates a subtraction “1”, the output 5000 of the calculation instruction storing flip-flop 5 also indicates a subtraction “1”, and the selection circuit 8 indicates the signal line.
The selection circuit 12 selects the signal line 10000 and stores it in the operation result storage register 9 and the overflow detection result storage flip-flop 13 respectively.

In this example, the operation without carry corresponding to addition and the operation with carry corresponding to subtraction are simultaneously performed by the two arithmetic units, and the overflow in the case without carry and the operation with carry are both detected at the same time.
The correct one is selected by the signal that selects either addition or subtraction. The calculation time can be shortened by such a method.

Next, a second embodiment will be described with reference to FIG. In the embodiment shown in FIG. 2, the first operand storage register 34, the second operand storage register 35, the operator 45 having the carry input “1”, the operators 55 and 65 having the carry input “0”, and the overflow detection circuit 4 are provided.
6, 56, selection circuits 47, 57, an overflow detection result storage flip-flop 49, and an operation result storage register 59.

The calculation of the fixed point number of the second embodiment is performed as follows.

The first operand A is stored in the first operand storage register 34,
The second operand B is stored in the second operand storage register 35, respectively. This first operand storage register 3
4, A and B stored in the second operand storage register 35 are separately output to the upper side 251, 351 and the lower side 252, 352.

The carry input “1” calculator 45 receives the upper outputs of the registers 34 and 35 as input, performs addition when there is a carry to the minimum digit, the overflow detection circuit 46 and the selection circuit.
Output to 57. The calculator 55 with carrier input “0” is a register
The outputs from the upper side of 34 and 35 are used as inputs, addition is performed when there is no carry to the minimum digit, and the results are output to overflow detection circuit 56 and selection circuit 57. Operator with carrier input “0”
Reference numeral 65 receives the lower outputs of the registers 34 and 35 as input, performs addition when there is no carry to the minimum digit, outputs the result to the operation result storage register 59, and simultaneously outputs the addition result carrier 653.

The arithmetic circuit 57 selects the output of the arithmetic circuit 45 and the arithmetic circuit 55 with the carrier output 653 of the arithmetic circuit 65 and selects the arithmetic result storage register 5
Output to 9. The selection circuit 47 selects the output of the overflow detection circuit 46 of the output from the arithmetic circuit 45 and the output of the overflow detection circuit 56 of the output from the arithmetic circuit 55 by the carrier output 653 of the arithmetic circuit 65, and stores it in the overflow detection result storage flip-flop 49. Store.

In this embodiment, the arithmetic unit is divided into a lower side and an upper side to obtain the upper side operation with and without the case, and the operation time is shortened by selecting the lower side carrier. is doing. Although the adder divided into two is taken as an example, an adder / subtractor configured to increase the number of divisions or to have a carry input at the lowest order and select with an addition / subtraction operation instruction signal is also conceivable.

(Effects of the Invention) As described above, according to the present invention, the fixed-point arithmetic operation and the operation for detecting the overflow of the arithmetic result are performed in an overlapping manner, whereby the overflow can be detected earlier. In addition, in this case, when an overflow is detected, a constant is added to the operation result, and the overflow can be detected earlier, so that the operation time can be shortened. Further, by using this arithmetic circuit for the processing of the instruction section of the floating point arithmetic circuit, there is an effect that the overflow of the exponent section can be detected early and the arithmetic time of the arithmetic operation in which a constant is put in the arithmetic result can be shortened. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an arithmetic unit according to the present invention, FIG. 2 is a block diagram showing a second embodiment of the present invention, and FIG. 3 is a block diagram of a conventional arithmetic unit. 1 …… First operand storage register 2 …… Inverter, 3,8,12 …… Selection circuit 4 …… Second operand storage register 5 …… Calculation instruction storage flip-flop 6 …… Calculator input “1” calculator 7 …… Carry input “0” calculator 9 …… Computation result storage register 10,11 …… Overflow detection circuit 13 …… Overflow detection result storage flip-flop 21 …… First operand storage register 22 …… Inverter 23,28… … Selection circuit 24 …… Second operand storage register 25 …… Operation instruction storage flip-flop 26 …… Carrier input “1” operator 27 …… Carry input “0” operator 29 …… Operation result storage register 30… … Overflow detection circuit 31 …… Overflow detection result storage flip-flop 34 …… First operand storage register 35 …… Second operand storage register 45 …… Carry input “1” Calculator 55,65 …… Carry input “0” calculator 46,56 …… Overflow detection circuit 47,57 …… Selection circuit 49 …… Overflow detection result storage flip-flop 59 …… Computation result storage register

Claims (1)

[Claims] 1. A first arithmetic unit performs an arithmetic operation when there is a carry input from a lower digit, and a second arithmetic unit performs an arithmetic operation when there is no carry input, and the first or second arithmetic operation is performed according to a selection instruction signal. A fixed-point arithmetic unit for selecting an arithmetic unit output result of the first arithmetic unit and storing the output result in an arithmetic result storage register; detecting a overflow from the output result of the first arithmetic unit; Overflow detection circuit, a second overflow detection circuit that detects the occurrence of an overflow from the output result of the second arithmetic unit, and the output result of the first arithmetic unit is selected by the selection instruction signal. When the output result of the second arithmetic unit is selected by the selection instruction signal, the second overflow detection circuit is selected. Computing device for a selection circuit for selecting the output of the flow detection circuit, characterized by comprising an overflow detection result storage flip-flop for storing the output of said selection circuit.