JP2508269B2 - Square root calculator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a square root calculation device. More specifically,
The present invention, when performing a square root operation on a system that performs floating point operations, uses a sticky bit (Sticky bi
t) relates to a new configuration of the device that performs the process of setting.

2. Description of the Related Art When performing a square root operation in a floating point arithmetic unit that performs rounding according to the IEEE standard, a flag is required to check whether or not there is a loss of precision. In other words, in the rounding process according to the IEEE standard, 2 bits for the rounding process are placed below the least significant bit of the mantissa part of the floating point format.
Bits (Guard bit and Round bit) and all bits below the Round bit are ORed (Sticky b
it) and are required. And these bits and four rounding modes (+00 direction, -00 direction, 0 direction,
Rounding-up processing or rounding-down processing is performed based on the (direction toward the nearest value).

FIG. 2 is a diagram showing a process of square root calculation processing. Here, it is assumed that the true operation result when the square root operation is performed is expressed with infinite precision, but in reality, the arithmetic unit does not operate with infinite precision, but the Guard Bit and Round bit in the mantissa part.
By finding the square root up to, and putting the logical OR of the Sticky bit lower than the Round bit, it can be made to appear as if it had infinite precision.

FIG. 6 and FIG. 7 respectively show a block diagram showing a configuration of an apparatus for executing the square root ascending method for obtaining 3 bits for rounding as described above, and a process executed on this apparatus. It is a flowchart shown.

First, as shown as a process 701 in FIG. 7, after storing the number of inputs A = a ₁ a ₂ ... a _n in the register 601 for number of inputs, the upper two digits of the number of inputs are R ₀ = a ₁ “1” is stored in the arithmetic register 602 and “1” in the arithmetic register 603 as a ₂ .

Next, as shown as process 702, the arithmetic register 602
The value of 603 is subtracted from
Store in 05.

Here, if the carry of the partial remainder register is “0”, that is, if the partial remainder is positive or zero, as shown as process 703, the operation result register is shifted to the left by 1 bit as shown at process 704, and Set "1" to the lower bit. Further, in the process 704, the register 601 is shifted to the left by 2 bits, the upper 2 bits are shifted to the lower 2 bits of the register 602, and the value of the register 605 is shifted to the left by 2 bits and stored in the register 602. Further, the value obtained by shifting the value of the register 606 by 2 bits to the left and adding “01” is stored in the register 603.

Next, as shown as operation 705, registers 672 through 60
Subtract the value of 3. Also, as shown as process 706, if the result of the operation performed in process 702, that is, the partial remainder is negative, the register for the operation result is shifted to the left by 1 bit and 0 is set to the least significant bit.

Next, as shown as a process 706, the register 601 is left-shifted by 2 bits, the upper 2 bits are stored in the register 602, and the value of the register 605 left-shifted by 2 bits is stored in the register 602. In addition, the value of register 606 is set to 2
The value obtained by adding “11” to the bit-shifted one is stored in the register 6.

Next, as shown as process 707, registers 602 and 603
And the value of are added.

By repeating these processes 703 to 707 for the number of digits in the register, the square root is obtained in the register 606 as shown in process 717.

Then, it is checked whether the accuracy of the calculation result has deteriorated.
That is, the value of the partial remainder register 605 is corrected as follows.

(A) If the value of the register 605 is 0, do nothing.

(B) If the value of the register 605 is positive, the values of the register 602 and the register 603 are added, as indicated by process 711.

(C) If the value of the register 605 is negative, the value obtained by shifting the value of the register 606 by 2 bits to the left and adding “01” is stored in the register 603, as shown as processing 712, and then,
Register 602 and register 603, shown as operation 713.
Is added.

The result corrected in the above manner is inspected as shown as process 714, and if “0”, S is displayed as shown as process 715.
The ticky bit 607 is set to "0", and if it is "1", the sticky bit 607 is set to "1" as shown as a process 715.

In the conventional device as described above, the processes from 710 to 716 for setting these precision deterioration flags are performed by the microprogram.

Problems to be Solved by the Invention Sticky, which is a flag for checking whether or not there is a loss of precision in the conventional square root arithmetic processing as described above
bit determines whether the value of the partial remainder after the operation is positive, negative, or zero, corrects the partial remainder when this is positive or negative, and whether the corrected value is zero. It was necessary to detect whether or not the sticky bit was set, and these were all done by microprograms. Therefore, there is a drawback that the number of steps of the microprogram is large and the number of execution clocks is increased.

Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, provide a specific circuit, reduce the load of processing by a microprogram, and provide a novel square root calculation device that shortens the processing time. Especially.

Means for Solving the Problem That is, according to the present invention, in a square root arithmetic unit for executing a square root arithmetic processing of an input number on a floating point arithmetic unit including rounding, a flag indicating that a precision loss has occurred, and a calculation A first zero detection circuit that detects that the partial remainder on the way is zero and a second zero detection circuit that detects that the number of inputs during the operation is zero are provided, and the flag is set to " If the partial remainder is zero and the number of inputs is also zero by the first and second zero detection circuits, the output of the first and second zero detection circuits is set to 1 ". There is provided a square root operation device having a function of resetting the flag to 0.

Action In contrast to the conventional square root operation device described above, the device according to the present invention detects the first zero detection circuit that detects that the partial remainder is zero, and that the number of inputs during the operation is zero. Its main feature is that it has a second zero detection circuit.

That is, by setting the logical sum of the value output by the first zero detection circuit 1 and the value output by the second zero detection circuit to the Sticky bit, the processing shown in FIG.
The processes shown as 710 to 716 are unnecessary, and
Setting ky bit is also easy. Therefore, both the number of steps and the number of clocks of the microprogram can be reduced.

Hereinafter, the present invention will be described more specifically with reference to the drawings, but the following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention.

Embodiment 1 FIG. 1 is a block diagram showing a configuration example of a square root calculation device according to the present invention.

As shown in FIG. 1, this square root arithmetic unit has an input number register 101, arithmetic registers 103 and 104, and an ALU.
105, partial remainder register 106, operation result register
109 and a flag 110. These configurations and functions are basically the same as those of the conventional square root operation device shown in FIG. Further, this square root arithmetic unit includes the first and second zero detection circuits 107 and 102, and the NAND gate 10
8 and.

Here, the first zero detection circuit 107 has a function of detecting that the partial remainder is zero. Further, the second zero detection circuit 102 has a function of detecting that the number of inputs during the calculation is zero. Further, the NAND gate 108
As will be described later, it has a function of setting the logical sum of the values output by the first zero detection circuit 107 and the second zero detection circuit 107 to the Sticky bit 110.

FIG. 2 is a diagram for explaining the sticky bit, as already described. Here, of the calculation results of infinite precision, 2 bits below the rounding precision are stored in Guard bit and Round bit. The Sticky bit stores a logical sum after the Round bit, and stores "1" when there is a loss of precision and "0" when there is no precision.

FIG. 3 is a flow chart showing the processing executed in the apparatus shown in FIG.

As shown as a process 301 in FIG. 3, first, the number of inputs is stored in the input number register 101 as A = a ₁ a ₂ ... A _n , and the upper two digits of the number of inputs are R ₀ = a ₁ a ₂ for arithmetic register 10
It is stored in 3, and 1 is further stored in the arithmetic register 104.

Next, as shown as process 302, the flag 110 is Sticky.
Set bit = "1".

Next, as shown as a process 305, the arithmetic register 103
The value of the register 104 is subtracted from the value of, and the result is stored in the partial remainder register 106.

Further, at this time, as shown as a process 304, it is checked whether the value of the partial remainder register 106 is “0”, and “0”
If the value of the output of the zero detection circuit 107 is "1" and the value of the input number register 101 is left-shifted by 2 bits is "0", the zero detector 10
The output of 2 is set to "1" and the outputs of the zero detection circuits 107 and 102 are set to "0" by the NAND gate 103 in the flag 110, that is, the Sticky bit. These processes 304 and 305 are executed by hardware.

Next, as shown as process 306, the value of the partial remainder register is checked, and if it is positive or "0", the following processes 307 and 308 are executed.

That is, first, as shown as a process 307, the operation result register 109 is shifted by 1 bit and "1" is set to the least significant bit. Then, the register 101 is shifted to the left by 2 bits, the upper 2 bits are stored to the lower 2 bits of the register 103, and the value of the register 106 is shifted to the left by 2 bits, and stored in the register 103. Also, register 109
The value obtained by adding "01" to the value obtained by shifting the value of 2 to the left by 2 bits is stored in the register 104. Next, as shown as process 308, the value in register 104 is subtracted from the value in register 103.

On the other hand, if it is detected in the process 306 that the partial remainder is negative, the following processes 309 and 310 are executed.

First, as shown as a process 309, the calculation result register 109 is left-shifted by 1 bit and "0" is set to the least significant bit. Then, the register 101 is shifted to the left by 2 bits, the upper 2 bits are stored to the register 103, and the value of the register 106 is shifted to the left by 2 bits to store it in the register 103.

Also, the value obtained by adding "11" to the value obtained by shifting the value of the register 109 by 2 bits to the left is stored in the register 104. Next, the value of the register 103 and the value of the register 104 are added.

The above processing from 306 to 310 is performed by processing 311
And 312, the number of digits in the register is repeated to obtain the square root of the number of inputs, as shown as process 313.

Embodiment 2 FIG. 5 is a block diagram showing another configuration example of the square root calculation device constructed according to the present invention.

As shown in FIG. 5, the configuration of this device is basically the same as that of the device of the first embodiment shown in FIG. 1, and a detailed description thereof will be omitted. It corresponds to Fig. 1 only by changing the first digit from "1" to "5".
As will be described later in detail, the apparatus of this embodiment has a configuration in which the square root is obtained by the return method.

FIG. 4 is a flow chart showing the steps of processing in the square root calculation device shown in FIG.

First, as shown as process 401 in FIG. 4, the number of inputs A
= A ₁ , a ₂ ··· a _n is used for the number of inputs and stored in register 501,
The upper two digits of the number input to the arithmetic register 503 are R ₀ = a ₁ , a ₂ , a
_{The value} is stored as _n , and “1” is stored in the register 504 for calculation.

Next, as processing 402, Sticky bit = 1 is set in the flag 501.

Next, as a process 403, the value stored in the register 504 is subtracted from the value stored in the arithmetic register 503, and the value is stored in the partial remainder register 506.

At this time, when the value of the partial remainder register 506 is “0”, the output of the zero detection circuit 507 is set to “1”, and the value of the input number register 501 left-shifted by 2 bits is set to “405” in processing 405. When it is "0", the output of the zero detection circuit 502 is set to "1", and the outputs of the zero detection circuits 507 and 502 are connected to the NAND gate 50.
Sticky bit by entering the flag 510 via 8
Is set to “0”. Here, the processes 404 and 405 are executed by hardware.

Next, if the value of the partial remainder register is positive or "0", the following processing is executed.

First, as the process 407, the register 509 for the calculation result is set to 1
Bit shift and set "1" to the least significant bit. Also, the register 501 is shifted left by 2 bits, and the upper 2 bits are transferred to the lower 2 bits of the register 503 and the register 506.
The value obtained by shifting the value of 2 to the left by 2 bits is stored in the register 503. Further, the value obtained by adding "01" to the value of the register 509 left-shifted by 2 bits is stored in the register 504. Next, as a process 409, the value of the register 504 is subtracted from the value of the register 503.

Further, if the calculation result performed in the process 403, that is, the partial remainder is negative, the following process is executed.

First, as a process 408, the operation result register 509 is left-shifted by 1 bit and "0" is set to the least significant bit.
Further, the register 501 is shifted to the left by 2 bits, the upper 2 bits are stored in the register 503, and the register 503 is further shifted to the left by 2 bits. Next, the value obtained by adding "01" to the value obtained by shifting the value of the register 509 by 2 bits to the left is stored in the register 504. Then, as a process 409, the value of the register 504 is subtracted from the value of the register 503.

As processes 410 and 411, processes 406 to 4 as described above are performed.
Repeat the processing up to 05 by the number of digits in the register to register
The square root of the input number is obtained in 509.

EFFECTS OF THE INVENTION As described above, the square root operation device according to the present invention includes the first zero detection circuit for detecting that the partial remainder is zero, and the first zero detection circuit for detecting that the number of inputs during the operation is zero. Two zero detection circuits, and the first and second
By setting the logical sum of the values output by the zero detection circuit of No. 1 to the Sticky bit, the processing conventionally performed by the microprogram is made unnecessary and the setting of the Sticky bit is facilitated. Therefore, in this device, both the number of steps and the number of clocks of the microprogram can be reduced in the square root calculation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a square root operation device according to the present invention, FIG. 2 is a diagram for explaining sticky bits, and FIG. 3 is shown in FIG. FIG. 4 is a flowchart for explaining the processing of the square root releasing method executed in the device, FIG. 4 is a block diagram showing another configuration example of the square root calculation device according to the present invention, and FIG. FIG. 6 is a flow chart for explaining the processing of the square root reverting method executed in the device shown in FIG. 6, FIG. 6 is a block diagram showing a configuration example of a conventional square root calculation device, and FIG. 7 is FIG. 6 is a flowchart illustrating processing of a square root release method executed in the apparatus shown in FIG. [Main reference numbers] 101 …… Input registers, 102,107 …… Zero detection circuit, 1
03, 104 ... Operation register, 105 ... ALU, 106 ... Partial remainder register, 108 ... NAND gate, 109 ... Operation result register, 110 ... Flag

Claims (1)

(57) [Claims] 1. A square root arithmetic unit for executing a square root arithmetic processing of an input number on a floating point arithmetic unit including rounding, a flag indicating that a precision loss has occurred, and a partial remainder in the middle of arithmetic operation being zero. And a second zero detection circuit for detecting that the number of inputs in the middle of the calculation is zero. The flag is set to "1" at the start of the calculation, and the first zero detection circuit And the second zero detection circuit, the partial remainder is zero,
If the number of inputs is also zero, the first and second
The square root calculation device having a function of resetting the flag to 0 according to the output of the zero detection circuit.