JPH033033A - Square root arithmetic unit - Google Patents

Abstract

PURPOSE:To reduce the load of processing based upon a microprogram by setting up a flag to '1' at the time of starting operation, and when the 1st and 2nd zero detecting circuits detect that a partial residual is zero and the number of inputs is also zero, resetting the flag to '0' with the outputs of the 1st and 2nd zero detecting circuits. CONSTITUTION:The arithmetic unit for square roots is provided with an input number register 101, arithmetic registers 103, 104, an ALU 105, a partial residual register 106, an operated result register 109, the 1st zero detecting circuit 107 provided with a flag 110 to detect the partial residual is zero, the 2nd zero detecting register 102 for detecting the number of inputs on the way of operation is zero, and an NAND gate 108. The NAND gate 108 sets up the OR of values outputted from the circuits 102 on the sticky bit 110. Consequently, processing executed by a microprogram can be omitted and the sticky bit can easily be set up.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a square root calculation device. More specifically, the present invention provides a method for reducing sticky bits when performing square root operations on systems that perform floating point operations.
This invention relates to a new configuration of a device that performs processing for setting bits.

Prior Art When performing a square root operation in a floating point arithmetic unit that performs rounding according to the IEEE standard, a flag is required to check whether there is a loss of precision. That is, IEEE
In standard rounding processing, two bits (Guard bit and Round
A sticky bit is required, which is the logical sum of all bits lower than the round bit. Then, rounding up or rounding down is performed based on four types of rounding modes (towards +00, -00, towards 0, and towards the nearest value).

FIG. 2 is a diagram showing the process of square root calculation processing. Here, it is assumed that the true result of the square root operation is expressed with infinite precision, but in reality, the arithmetic unit does not perform the operation with infinite precision, but instead uses Guarcl Bit,
Find the square root up to Round bit, 5ticky
By inserting a logical sum lower than the round bit into the bit, it can be made to appear as if it had infinite precision.

FIGS. 6 and 7 are block diagrams showing the configuration of a device that executes the square root pull-off method for obtaining 3 bits for rounding as described above, and the processing executed on this device, respectively. FIG.

First, as shown as process 701 in FIG. 7, the number of inputs is entered in the input number register 601 as follows:
After storing 7, the upper two digits of the input number are set as R2H,a2 and "l" is stored in the calculation register 602 and the calculation register 603, respectively.

Next, as shown in process 702, the value in the calculation registers 602 and 603 is subtracted, and the partial remainder is stored in the partial remainder register 605.

Here, as shown in process 703, if the carry in the partial remainder register is b positive or zero, as shown in process 704, the operation result register is shifted to the left by 1 bit, and the lowest bit is set to ``bit''. Also, in process 704, the register 601 is shifted to the left by 2 bits, the upper 2 bits are transferred to the lower 2 bits of the register 602, and the register 601 is shifted to the left by 2 bits.
The value of 5 shifted to the left by 2 bits is stored in register 602.
Store it in Further, the value of the register 606 is shifted to the left by 2 bits and "0 bit" is added to the result and stored in the register 603.

Next, as shown in process 705, the value of register 603 is subtracted from register 672. Further, as shown in process 706, if the operation result performed in process 702, that is, the partial remainder is negative, the operation result register is shifted to the left by 1 bit, and the least significant bit is set to 0.

Next, as shown in process 706, the register 601 is shifted to the left by 2 bits, and the upper 2 bits are transferred to the register 602.
Then, the value of register 605 is shifted to the left by 2 bits and stored in register 602, respectively.

Further, the value obtained by shifting the value of the register 606 to the left by 2 bits and adding "l 1 " is stored in the register 603.

Next, as shown in process 707, the values of registers 602 and 603 are added.

By repeating these processes 703 to 707 for the number of digits in the register, the square root is obtained in the register 606 as shown in process 717.

Next, check whether the accuracy of the calculation result has decreased. That is, the correction is made as follows using the value of the partial remainder register 605.

(a) If the value of register 605 is 0, nothing is done.

) If the value of register 605 is positive, the values of register 602 and register 603 are added as shown in process 711.

(C) If the value of the register 605 is negative, as shown in process 712, the value of the register 606 is shifted to the left by 2 bits and 01'' is added and stored in the register 603, and then as shown in process 713 As shown, register 60
2,! Add the value of NIR register 03.

The result corrected as above is checked as shown in process 714, and if it is 60'', the 5ticky bit 607 is set to "0" as shown in process 715,
If it is “1”, process 715 as shown in 5tick.
Set ybit 5Q7 to “P”.

Note that in the conventional apparatus as described above, the processes 710 to 716 for setting these flags for decreasing precision are performed by a microprogram.

Problems to be Solved by the Invention In the conventional square root arithmetic processing as described above, the 5tic flag is used to check whether there is a drop in accuracy.
The ky bit is used to determine whether the value of the partial remainder after the completion of the operation is positive, negative, or zero, to correct the partial remainder if it is positive or negative, and to determine whether the corrected value is zero. It is necessary to detect whether or not it is true, and to set 5 ticky bits, all of which are performed by a microprogram. Therefore, there is a drawback that the number of microprogram steps is large and the number of locks to be executed increases.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a novel square root arithmetic device which solves the above-mentioned problems of the prior art, reduces the burden of processing by microprograms, and shortens processing time by providing a specific circuit. There is a particular thing.

Means for Solving the Problems According to the present invention, in a square root arithmetic unit that executes square root arithmetic processing of an input number on a floating point arithmetic unit including rounding, a flag indicating that precision loss has occurred, and an operation The first step is to detect that the intermediate partial remainder is zero.
and a second zero detection circuit that detects that the number of inputs during the calculation is zero, sets the flag to "bi" at the start of the calculation, and performs the first and second zero detection circuit. The circuit has a function of resetting the flag to O by the outputs of the first and second zero detection circuits when the partial remainder is zero and the number of inputs is also zero. A square root calculation device is provided.

Function: In contrast to the conventional square root calculation device described above, the device according to the present invention includes a first zero detection circuit that detects that the partial remainder is zero, and a first zero detection circuit that detects that the number of inputs during the calculation is zero. Its main feature is that it is equipped with a second zero detection circuit.

That is, the logical sum of the value output by the first zero detection circuit 1 and the value output by the second zero detection circuit is calculated as 5ticky b
In the prior art, by setting it to
The processes shown as processes 710 to 716 in the figure become unnecessary, and furthermore, the setting of 5 ticky bits becomes easy.

Therefore, both the number of microprogram steps and the number of clocks can be reduced.

Hereinafter, the present invention will be described in more detail with reference to the drawings, but the following disclosure is only one embodiment of the present invention, and does not limit the technical scope of the present invention in any way.

Embodiment 1 FIG. 1 is a block diagram showing an example of the configuration of a square root calculation device according to the present invention.

As shown in FIG. 1, this square root calculation device includes an input number register 101, calculation registers 103 and 10.
4, an ALU 105, a partial remainder register 106, an operation result register 109, and a flag 110. These structures and functions are basically the same as the conventional square root calculation device shown in FIG. moreover,
This square root calculation device includes first and second zero detection circuits 107 and 102 and a NAND gate 108.

Here, the first zero detection circuit 107 has a function of detecting that the partial remainder is zero.

Further, the second zero detection circuit 102 has a function of detecting that the number of inputs during calculation is zero.

Furthermore, the NAND gate 108 has a first
It has a function of setting the logical sum of the values output by the zero detection circuit 107 and the second zero detection circuit 107 to 5ticky bitllQ.

As already explained, Figure 2 shows 5 ticky bits.
FIG. Here, of the infinite precision calculation results, 2 bits below the rounding precision are stored in the Guard bit and Round bit. Also, 5tic
The ky bit stores the logical sum after the round bit, and if there is a loss of ζ precision, "1" is stored, and if there is no loss, "0°" is stored.

FIG. 3 is a flowchart showing the processing executed in the apparatus shown in FIG.

As shown as process 301 in FIG. 3, first, the input number is set to A=ata2...al and the input number register 10
1, store the upper two digits of the input number Ro''a and a2 in the calculation register 103, and further store the calculation register 10
Store 1 in 4.

Next, as shown in process 302, 5ticky bit="1" is set in the flag 110.

Next, as shown in process 303, the value of the register 104 is subtracted from the value of the calculation register 103, and the result is stored in the partial remainder register 106.

At this time, as shown in process 304, it is checked whether the value of the partial remainder register 106 is "0",
II OII, as shown in process 305, the output of the zero detection circuit 107 is set to "l", and the value of the input number register 101 is shifted to the left by 2 bits, and the value is 0.
'', the output of the zero detector 102 is set as Pavi, and the outputs of the zero detection circuits 107 and 102 are set as the NAND gate 10.
8 sets the flag 110, ie, the 5ticky bit, to "0". These processes 304 and 305 are executed by hardware.

Next, as shown in process 306, the value of the partial remainder register is checked, and if it is positive or "0'", the following processes 307 and 308 are executed.

That is, first, as shown in process 307, the operation result register 109 is shifted by one bit, and the least significant bit is set to "1". Subsequently, the register 101 is shifted to the left by 2 bits, the upper 2 bits are transferred to the lower 2 bits of the register 103, and the value of the register 106 is shifted to the left by 2 bits and stored in the register 103, respectively. Also, the value of register 109 is shifted to the left by 2 bits.
01'' is added and stored in the register 104. Next, as shown in process 308, the value of the register 104 is subtracted from the value of the register 103.

On the other hand, if it is detected in process 306 that the partial remainder is negative, the following processes 309 and 310 are executed.

First, as shown in process 309, the operation result register 109 is shifted to the left by 1 bit, and the least significant bit is set to "0".
Then, register 101 is shifted to the left by 2 bits, the upper 2 bits are stored in register 103, and the value of register 106 is shifted to the left by 2 bits and stored in register 103, respectively.

Further, the value obtained by shifting the value of register 109 to the left by 2 bits and adding 1 is stored in register 104. Next, the value of register 103 and the value of register 104 are added.

By repeating the above processes 306 to 310 as many times as the number of digits in the register, as shown as processes 311 and 312, as shown as process 313,
The square root of the input number is obtained.

Embodiment 2 FIG. 5 is a block diagram showing another example of the configuration of a square root calculation device configured according to the present invention.

As shown in FIG. 5, the configuration of this device is basically the same as the device of Example 1 shown in FIG. The first digit is “
It corresponds to FIG. 1 only by changing from l'' to '5''. In addition, as will be specifically described later, in the apparatus of this embodiment,
The structure is such that the square root is obtained using the back-back method.

FIG. 4 is a flowchart showing the process of the square root calculation device shown in FIG.

First, as shown as process 401 in FIG. 4, after storing the number of inputs A=a,, a2 . a2+ah, and “l” is stored in the calculation register 504.

Next, as process 402, 5ticky is set in the flag 501.
Set bit=1.

Next, as process 403, the value stored in the register 504 is subtracted from the value stored in the calculation register 503,
The value is stored in the partial remainder register 506.

At this time, if the value of the partial remainder register 506 is "0", as a process 405, the output of the zero detection circuit 507 is set to "B", and the value of the input number register 501 is shifted to the left by 2 bits, and the value is "0". ”, the output of the zero detection circuit 502 is set to “1”, and the outputs of the zero detection circuits 507 and 502 are input to the flag 510 via the NAND gate 508, thereby setting 5tickybit to “0”. Processes 404 and 405 are executed by hardware.

Next, if the value of the partial remainder register is positive or "°0'", the following processing is executed.

First, as a process 407, the register 50 for the operation result is
9 is shifted by 1 bit, and "B" is placed in the least significant bit. Also, the register 501 is shifted to the left by 2 bits, the upper 2 pin points are shifted to the lower 2 bits of register 503, and the value of register 506 is shifted to the left by 2 bits. are stored in the registers 503.Furthermore, the registers 509
The value obtained by shifting the value of 2 bits to the left and adding 01" is stored in the register 504. Next, in process 409, the value of the register 504 is subtracted from the value of the register 503.

Further, if the calculation result performed in process 403, that is, the partial remainder is negative, the following process is executed.

First, as processing 408, the operation result practical register 509
is shifted to the left by 1 bit, and the least significant bit is set to "0". Also, the register 501 is shifted to the left by 2 bits, the upper 2 bits are stored in the register 503, and the register 503 is further shifted to the left by 2 bits.

Next, the value of register 509 is shifted to the left by 2 bits and 01'' is added to the result and stored in register 504.

Subsequently, in process 409, the value of the register 504 is subtracted from the value of the register 503.

Processes 410 and 411 include process 40 as described above.
By repeating the processes from 6 to 409 for the number of digits in the register, the square root of the input number is obtained in the register 509.

As described in detail, the square root calculation device according to the present invention includes a first zero detection circuit that detects that the partial remainder is zero, and a first zero detection circuit that detects that the number of inputs during the calculation is zero. 2
and a zero detection circuit, and the logical sum of the values output from these first and second zero detection circuits is calculated as 5 ticky bits.
By setting the 5ticky bit to
It is easy to set up. Therefore, with this device, both the number of microprogram steps and the number of clocks can be reduced during square root calculation.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an example of the configuration of a square root arithmetic device according to the present invention, and FIG.
), FIG. 3 is a flowchart illustrating the processing of the square root pull-off method executed in the apparatus shown in FIG. 1, and FIG. 5 is a block diagram showing another configuration example; FIG. 5 is a flowchart illustrating the processing of the square root subtracting method executed in the device shown in FIG. 4; FIG. 6 is a conventional square root calculating device. FIG. 7 is a flowchart illustrating the processing of the square root pull-off method executed in the apparatus shown in FIG. 6. FIG. [Main reference numbers] 101...Manual register, 102.107...Zero detection circuit, 103.104
...Arithmetic register, 105...ALU. 106...Partial remainder register, 108...NAND gate, 109...Operation result register, 110...Flag

Claims (1)

[Claims] In a square root arithmetic unit that performs square root arithmetic processing of an input number on a floating point arithmetic unit that includes rounding, a flag indicating that precision loss has occurred and a partial remainder in the middle of the operation are zero. a first zero detection circuit that detects that the number of inputs is zero during the calculation, and a second zero detection circuit that detects that the number of inputs during the calculation is zero, sets the flag to "1" at the start of the calculation, and If the partial remainder is zero and the number of inputs is zero by the first and second zero detection circuits, the flag is reset to 0 by the outputs of the first and second zero detection circuits. A square root calculation device characterized by having a function.