JPS6224816B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic processing device, and more particularly to an improvement in a device that performs multiplication of binary coded decimal numbers.

It is generally well known that binary coded decimal numbers are multiplied by repeated addition or subtraction. This conventionally commonly used binary system 10
FIG. 1 shows an example of the configuration of a device that performs base number multiplication.
In Figure 1, register 1 stores intermediate results.
The register 2 that stores the multiplier and the signal line 31, 3
2 is connected to the input of the arithmetic unit 5. The output of the arithmetic unit 5 is sent to the register 1 again via the signal line 30.
connected to. Register 1 is also connected to the input of shifter 4 by signal line 29, and the output of shifter 4 is connected to register 1 again by signal line 28. An arbitrary digit of the multiplicand storage register 3 is selected by the digit position indicating counter 8 and is connected to one input of the arithmetic unit 6 via the signal line 23 . register 1
The least significant digit of is also connected to the same input of the arithmetic unit 6 via the signal line 33. A constant generated by a constant generation circuit 7 is connected to the other input of the arithmetic unit 6 via a signal line 24. The output of the arithmetic unit 6 is stored in an arbitrary digit indicated by the digit position indicating counter 8 in the register 3 via the signal line 25. Further, the output of the arithmetic unit 6 is connected to the 0 detection circuit 12 via a signal line 26, and the result of 0 detection is given to the control device 13 via a signal line 27. The memory 9 is a memory into which multipliers and multiplicands are read and products are written, and can be read and written using addresses generated by the address generator 10. That is, the contents of register 3 are transmitted to signal line 36.
The contents read from the memory 9 can be written to the register 2 via the signal line 21, and the contents read from the memory 9 can be written to the register 2 via the signal line 21.
It is written to register 3 via. The control circuit 13 controls the address generator 10, reading and writing of the memory 9, inputs to the register 1, register 2, and register 3, the shifter 4, the arithmetic unit 5,
It controls the arithmetic unit 6, constant generation circuit 7, and digit position instruction counter 8.

The operation of this arithmetic processing device is executed by the following six execution cycles.

The first execution cycle is the reading of the multiplicand from memory 9. The contents indicated by the address generated by the address generator 10 are read from the memory 9 and stored in the register 3 via the signal line 22.

The second execution cycle is the reading of the multiplier from memory 9. The contents indicated by the address generated by the address generator 10 are read from the memory 9 and stored in the register 2 via the signal line 21.

In the third execution cycle, the digit position instruction counter 8
1 digit of the register 3 shown by is placed on the input of the arithmetic unit 6. The constant generation circuit 7 generates 0 and puts it on the other input of the arithmetic unit 6. Arithmetic unit 6 performs an addition operation and outputs the result to signal line 26.
That is, the contents of the digit indicated by the digit position instruction counter 8 of the register 3 are output to the signal line 26 as they are.

The fourth execution cycle is an arithmetic cycle. The contents of register 1 and register 2 are input to arithmetic unit 5 via signal lines 31 and 32, respectively, and addition is performed. The result is written to register 1 via signal line 30. At the same time, one digit in the register 3 indicated by the digit position indication counter 8 is input to the arithmetic unit 6. Arithmetic unit 6 and constant generation circuit 7 subtract 1 from this value, and the result is again inserted into the digit indicated by digit position indication counter 8 in register 3 via signal line 25.

The fifth execution cycle is a cycle in which one digit of the determined product is stored in the register 3. The lower one digit in the register 1 is input to the arithmetic unit 6 via the signal line 33, where it is added to 0 generated by the constant generation circuit 7, and the result is sent to the register 3 via the signal line 25. It is inserted into the digit indicated by the digit position indication counter 8 in . Thereafter, the digit position indication counter is decremented by 1 to indicate the next digit to be processed.

The sixth execution cycle is a cycle in which the determined product is written into the memory 9. The contents of register 3 are transmitted to address generator 1 in memory 9 via signal line 36.
It is written to the location indicated by the address generated by 0.

Next, the operation will be explained in detail using a specific example. Second
The figure shows the flow of the aforementioned execution cycle and the contents of registers 1, 2, and 3 when (1002)×(0004) is executed by the arithmetic processing device of FIG.

Prior to the operation, all digits of intermediate result storage register 1 must be set to 0. This can be easily obtained by forcibly setting the input of the shifter 4 or the arithmetic unit 5 to 0 and writing that value to the register 1.

Initially, the control circuit 13 controls the memory 9 and the address generator 10 to execute the first execution cycle, whereby the multiplicand (1002) is stored in the register 3. Next, a second execution cycle is started and the multiplier (0004) is stored in register 2. Subsequently, a third execution cycle is started,
The least significant digit in the register 3 is passed through the arithmetic unit 6 and placed on the signal line 26. The control circuit 13 determines whether to perform the fourth execution cycle next depending on whether the value of the signal line 26 is 0 or not. In the example in Figure 2,
Since the value of the signal line 26 is "2", the fourth execution cycle is activated. The fourth execution cycle is continuously executed by the control circuit 13 until the signal line 26 becomes 0. When the signal line 26 becomes 0, the fifth
An execution cycle is executed, and one digit of the product found in the lowest register of register 1 is transferred to register 3, and register 1 is shifted to the right by one digit. Then again the third
A run cycle is executed. In the example of FIG. 2, the second digit of register 3 is 0, so the signal line 26 becomes 0, and the fifth execution cycle is started this time. Thereafter, similar operations are repeated for each digit in register 3. When the calculations for all digits of register 3 are completed, the product has been found in register 3, so a sixth execution cycle is started and the product is written into memory 10. If the multiplicand has a length that does not fit in register 3, the first execution cycle is started to read the remainder of the multiplicand from memory 9, and the same goes for the new multiplicand that has been taken into register 3. The operation is repeated.

As described above, in the conventional method, even if the value of the digit of the multiplicand is 0, a cycle for detecting 0 and a cycle for transferring the calculated product by one digit are required. In calculations, 0 often appears in the multiplicand, and the conventional method described above has a problem in improving performance.

An object of the present invention is to eliminate the above-mentioned conventional problems, and to detect the 0 digit and the number of digits in the multiplicand when performing multiplication of binary coded decimal numbers. An object of the present invention is to provide an arithmetic processing device that has the effect of performing digit arithmetic at a higher speed.

Therefore, the feature of the present invention is that the zero digit and its number of digits are detected from any position of the multiplicand during the calculation, and the intermediate result is shifted according to the number of digits. The product associated with the 0 digit can be found more quickly.

Next, one embodiment of the present invention will be described in detail using the drawings.

FIG. 3 is a block diagram of an embodiment of the present invention. In FIG. 3, the output of register 3 is connected to signal line 38.
It is connected to the 0 digit detection circuit 11 via. Further, the digit position indication counter 8 is connected to the 0 digit detection circuit 11 through a signal line 39. The zero digit detection circuit 11 sends a signal indicating whether or not there is a 0 in the digit of the register 3 indicated by the digit position indication counter 8 to the control circuit 13 via the signal line 40. At the same time, the zero digit detection circuit 11 sends the number of consecutive zero digits to the control circuit 13 via the signal line 41. The configuration other than these is the same as in FIG. 1.

The feature of this arithmetic processing device is that the 0 digit detection circuit 11 eliminates the need for the conventional third execution cycle when there are consecutive 0 digits; This is performed by the next five execution cycles. That is, the first execution cycle is the reading of the multiplicand from the memory 9. The second execution cycle is the reading of the multiplier from memory 9. Next, the process immediately shifts to the fourth execution cycle, in which the arithmetic unit 5 adds registers 1 and 2, and the arithmetic unit 6 subtracts one digit in register 3. The fifth execution cycle is a cycle in which one digit of the determined product is transferred from the lower register of register 1 to register 3. The sixth execution cycle is a cycle in which the calculated product in the register 3 is written to the memory 10.

Next, the operation of the present arithmetic processing device will be explained using a specific example. Figure 4 shows the flow of the above execution cycle when executing (1002) x (0004), and the register 1,
This shows the contents of 2 and 3.

Prior to the operation, all digits of the intermediate result storage register 1 are set to 0. First, the control circuit 13
controls the memory 9 and address generator 10 to execute the first execution cycle. As a result, the multiplicand is stored in register 3. A second execution cycle is then started and the multiplier is set in register 2.
is stored in

Next, the 0 digit detection circuit 11 detects whether the digit indicated by the digit position indication counter 8 is 0 or not. If there is a digit that is 0, a fifth execution cycle is performed and the digit is 0. If the digit does not exist,
A fourth execution cycle is performed. In the example in Figure 4,
Initially, the digit position indication counter 8 indicates the rightmost digit of the register 3, and in this case, the value is "2", so the fourth execution cycle is started. The fourth execution cycle is continuously executed by the control circuit 13 until the signal line 26 becomes 0.

When the signal line 26 becomes 0, the fifth execution cycle is executed and 1 of the product found in the lowest register 1 is stored.
Transfer the digit to register 3 and shift register 1 to the right by one digit.

Thereafter, the 0 digit detection circuit 11 again determines whether to execute the fourth execution cycle or the fifth execution cycle. In the example of FIG. 4, the digit position indication counter 8 indicates the second digit from the right of the register 3, and this digit and the next digit are 0. As a result, the signal line 40 indicates that there is a 0 digit, and the signal line 41 sends the number of 0 digits to the control circuit 13. The control circuit executes the fifth cycle through a signal line 40, and determines how many consecutive cycles of the fifth cycle are to be executed through a signal line 41. In the example shown in FIG. 4, since the zero-digit number "2" is sent out through the signal line 41, the fifth cycle is executed two times in a row.

Thereafter, similar operations are repeated for each digit in register 3.

When the operations for all digits in register 3 are completed, the product has been found in register 3, so a sixth execution cycle is started and the product is written into memory 10. Thereafter, if the multiplicand has a length that does not fit in register 3, a first execution cycle is started to read the remainder of the multiplicand from memory 10, and the same goes for any new multiplicands that are subsequently taken into register 3. The operation of
Repeated.

As is clear from comparing FIG. 2 and FIG. 4, by having the 0 digit detection circuit 11 as shown in FIG. This eliminates the need to perform multiplication at high speed when the multiplicand includes 0.

FIG. 5 shows a specific example of the configuration of the zero digit detection circuit 11 shown in FIG. The register 3 and digit position counter 8 are the same as those described in FIG. In FIG. 5, it is assumed that the register 3 has a width of four digits, but in general, the width may be more or less than four digits. The digit position instruction counter 8 is
It has a width of 2 bits so that the 4 digit positions of register 3 can be specified. The width of this digit position instruction counter 8 is also arbitrary like the width of the register 3.

FIG. 6 shows the correspondence between the contents of the digit position counter 8 and the digit positions of the register 3 in the example of FIG. In FIG. 6, the digits of register 3 are represented in order from the left as (00), (01), (10), and (11). This expression may be any code as long as it can clearly determine the digit position of register 3.

Returning to FIG. 5, the register 3 is connected to the 0 detection circuits 50 to 53 via the signal line 38. The 0 detection circuits 50 to 53 detect 0 for each digit, and if
If all the digits are 0, "1" is output, otherwise "0" is output to signal lines 72-75.
The NOT gates 55 and 56 are connected to the signal line 7, respectively.
2, 73 is negated and output to signal lines 80, 81.

On the other hand, the digit position instruction counter 8 is connected to the decoder 54 via a signal line 39. Decoder 54 outputs decoding results to signal lines 76-49. FIG. 6 also shows the operation of the decoder 54. That is, in Fig. 6, the input of the decoder is
b ₀ and b ₁ , and the outputs are y ₀ , y ₁ , y ₂ , and y ₃ .
y ₀ to y ₃ are signal lines 76 to 79 in FIG. 5, respectively.
It corresponds to As shown in FIG. 6, the decoder 54 sets 1 to y ₀ if the input is (00), 1 to y ₁ if the input is (01), and 1 to y ₂ if the input is (10). If yes ₃
Outputs 1 for each.

The signal lines 72 to 81 in FIG.
7 to 67 and a gate group consisting of OR gates 68 to 71. These gate groups are
A signal line 40 and a signal line 41 are output. Signal lines 40 and 41 are the same as described in FIG. Among these, the signal line 41 is composed of two signal lines 42 and 43 in order to indicate the number of digits that are 0. In the example in Figure 5, the width of register 3 is 4 digits, so 2 bits are sufficient to represent the number of consecutive 0 digits, but if the width of register 3 is larger than 4 digits, then , signal line 41
consists of three or more signal lines.

FIG. 7 is a diagram illustrating in detail the operation of the 0-digit detection circuit shown in FIG. 5. In FIG. 7, the digit position instruction counter 8 is connected to b ₀ , b ₁ , and the signal lines 72 to 72 in FIG.
75 is expressed as x ₀ , x ₁ , x ₂ , x ₃ , the signal line 41 is expressed as c ₀ , c ₁ , and the signal line 40 is expressed as d. When b ₀ and b ₁ are (00) (y ₀ =1), if x ₀ is 0, d is output as 0 because an addition cycle of the multiplier and the intermediate result is required. If x ₀ is 1, there is one 0 digit, so c ₀ and c ₁ have (00), d
1 is output. When b ₀ and b ₁ are (01) (y ₁
= 1), if x ₁ is 0, a 0 is output to d because an addition cycle of the multiplier and the intermediate result is required. When x ₁ is 1 and x ₀ is 0, there is one 0 digit, so (00) is output to c ₀ and c ₁ and 1 is output to d. If x ₁ is 1 and x ₀ is also 1, there are two 0 digits, so (01) is output to c ₀ and c ₁ and 1 is output to d. b ₀ and b ₁ are (10) (y ₂ = 1) (11) (y ₃ = 1)
Similarly, when there is a 0 digit,
1 is output to d, when it does not exist, 0 is output to d, and when 0 digit exists, 1 digit is 0 in c ₀ and c ₁ .
(00) if two consecutive digits are 0, (01) if two consecutive digits are 0, (10) if three consecutive digits are 0, consecutive 4
When the digit is 0, (11) is output. These conditions are AND gates 57-67 and OR gates 68-71.
It is taken by

In this way, by using the states of the output signal lines 40 and 41 and executing the fifth execution cycle as many times as there are 0 digits in the multiplicand, a binary coded decimal number when the multiplicand includes a 0 digit is obtained. It is possible to realize an arithmetic processing device that can perform multiplication at high speed.

FIG. 8 shows another specific example of the configuration of the 0-digit detection circuit. In FIG. 8, as in FIG. 5, register 3 is 4.
The case where the digit and digit position detection circuit 8 is 2 bits is shown. In FIG. 8, register 3, digit position instruction counter 8, signal lines 38 to 39, 0 detection circuit 50
53, decoder 54, signal lines 72-75, and signal lines 76-79 are the same as those described in FIG. AND gates 82 to 88 and OR gate 89 connect signal lines 72 to 75 and signal lines 76 to
79 as an input, and outputs a signal indicating whether or not there is a 0 digit in the register 3 to the signal line 40. The signal line 41 indicating the number of 0 digits is directly connected to the signal lines 90 to 90 connected to the output of the digit position indicating counter.
91.

FIG. 9 is a diagram illustrating in detail the operation of the 0-digit detection circuit shown in FIG. 8. b ₀ , b ₁ , x ₀ ~ x ₃ ,
The meanings of c ₀ , c ₁ , and d are the same as in FIG. 7. _b0 ,
When b ₁ is (00), if x ₀ is 1, (00) is output to c ₀ and c ₁ , and 1 is output to d. If x ₀ is not 1, 0 is output to d. When b ₀ and bA are (01), when x ₀ and x ₁ are originally 1, c ₀ ,
(01) is output to _c1 and 1 is output to d. At other times, 0 is output to d. b ₀ and b ₁ are
In (10), when x ₀ , x ₁ , and x ₂ are all 1,
(10) is output to c ₀ and c ₁ , and 1 is output to d. At other times, 0 is output to d. b ₀ and b ₁ are
In (11), when x ₀ , x ₁ , x ₂ , x ₃ are all 1,
(11) is output to c ₀ and c ₁ , and 1 is output to d. At other times, 0 is output to d.

The 0 digit detection circuit shown in FIG. 8 differs from the 0 digit detection circuit shown in FIG. 5 in that the 0 digit detection circuit shown in FIG.
0 becomes 1, and the number of digits of 0 at that time is output to the signal line 41. Therefore, the fifth cycle can be executed continuously without executing the third execution cycle when the upper digits of the register 3 are consecutively 0's. Generally, there are many consecutive 0 digits at the top of the multiplicand, so the embodiment shown in FIG. 8 can also provide sufficient effects.

As described above, in the embodiment, the arithmetic unit 6 used when transferring the lower part of the intermediate result storage register 1 to the register 3
Although the width has been described as being one digit, the width may be two digits or even larger.
Increasing this width will require fewer cycles to transfer the product from register 1 to register 3, and if the multiplicand has many consecutive 0s,
Calculations can be performed faster.

Further, in the embodiment, the multiplicand and the calculated product are stored in the same register 3, but they may be configured in separate registers. In addition, in the calculation cycle, the calculation unit used to subtract 1 from one digit of the multiplicand and the path for transferring the calculated product from intermediate result storage register 1 to register 3 are shared by calculation unit 6. , may be configured separately.

As described above, in the present invention, by detecting the number of 0 digits and the number of 0 digits in the multiplicand, the product is extracted from the intermediate result storage register by the number of digits. Cycles can be made consecutive, and operations on 0 digits in the multiplicand can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional arithmetic processing device that performs multiplication of binary coded decimal numbers, FIG. 2 is a diagram explaining an example of the operation according to FIG. 1, and FIG. 3 is a diagram showing an embodiment of the present invention. 4 is a diagram for explaining an example of the operation according to FIG. 3, FIG. 5 is a specific circuit diagram of the 0 digit detection circuit in FIG. 3, and FIGS. 6 and 7 are for explaining the operation of FIG. 5. , FIG. 8 is another specific circuit diagram of the 0-digit detection circuit in FIG. 3, and FIG. 9 is a diagram for explaining the operation of FIG. 8. 1... Intermediate result register, 2... Multiplier register, 3... Multiplicand register, 4... Shifter, 5...
...Arithmetic unit, 6...Arithmetic unit, 7...Constant generation circuit,
8...Digit position instruction counter, 9...Memory, 10
... Address generator, 11 ... 0 digit detection circuit, 1
2...0 detection circuit, 13...control circuit.

Claims (1)

[Claims] 1 A register that stores the multiplicand, a register that stores the multiplier, and a register that stores the intermediate result.
an arithmetic unit that operates on the contents of the register that stores the multiplier and the register that stores the intermediate result; a shifter that shifts the contents of the register that stores the intermediate result; and a shifter that sequentially shifts the digits of the register that stores the multiplicand. A counter for indicating the digit position to be instructed, a computing unit that selects and computes the digit indicated by the counter, and a computing unit that selects and computes the digit indicated by the counter, until the output of the computing unit reaches a predetermined value.
An arithmetic processing device comprising a control circuit for repeatedly calculating the contents of the multiplier storage register and the intermediate result storage register for a corresponding digit, and performing multiplication of binary coded decimal numbers by repeating addition or subtraction; A 0 digit detection circuit is provided to detect a 0 digit of the multiplicand of the multiplicand storage register and the number of 0 digits consecutive to the digit, and the 0 digit detection circuit detects the 0 digit of the multiplicand and the number of digits thereof,
The arithmetic processing device is characterized in that the control circuit performs control to obtain a product from the intermediate results while shifting the contents of the intermediate result storage register by the number of digits using the shifter.