JPS5569850A - Decimal multiplication system - Google Patents

Decimal multiplication system

Info

Publication number
JPS5569850A
JPS5569850A JP14331378A JP14331378A JPS5569850A JP S5569850 A JPS5569850 A JP S5569850A JP 14331378 A JP14331378 A JP 14331378A JP 14331378 A JP14331378 A JP 14331378A JP S5569850 A JPS5569850 A JP S5569850A
Authority
JP
Japan
Prior art keywords
order digits
multiplier
low
circuit
multiplication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14331378A
Other languages
Japanese (ja)
Inventor
Hisao Nakajo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14331378A priority Critical patent/JPS5569850A/en
Publication of JPS5569850A publication Critical patent/JPS5569850A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase a multiplication speed with multiplication loop reduced in number by detecting the number of "O"s of high-order digits and low-order digits of a multiplier, by finding the partial product with the number of low-order digits removed from that of multiplier loops, and then by storing a memory with this partial products shifted by the number of low-order digits.
CONSTITUTION: A multiplier circuit consists of multiplier memory circuit 20, gate circuit 21, register 22 stored with binary data from circuit 21, and subtracter 23 subtracting the contents of register 22, one by one. Further, this is provided with detector 24 for a check on "0" among outputs of them, circuits 25 and 26 detecting "0" of high-order digits and low-order digits, registers 27 and 30 stored with detection outputs, gate 31, and subtracter 32 controlling the number of multiplier digit loops in multiplication operation. Furthermore, counting register 33, detector 34 detecting the end of a loop, and control circuit 35 obtaining the partial product are provided. The above-mentioned constitution provides arithmetic with the number of "0"s of high-order digits and low-order digits removed, reducing multiplication loops in number.
COPYRIGHT: (C)1980,JPO&Japio
JP14331378A 1978-11-22 1978-11-22 Decimal multiplication system Pending JPS5569850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14331378A JPS5569850A (en) 1978-11-22 1978-11-22 Decimal multiplication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14331378A JPS5569850A (en) 1978-11-22 1978-11-22 Decimal multiplication system

Publications (1)

Publication Number Publication Date
JPS5569850A true JPS5569850A (en) 1980-05-26

Family

ID=15335858

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14331378A Pending JPS5569850A (en) 1978-11-22 1978-11-22 Decimal multiplication system

Country Status (1)

Country Link
JP (1) JPS5569850A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57172445A (en) * 1980-12-24 1982-10-23 Honeywell Inf Systems Information processor executing decimal multiplication using read only memory
JPS5892037A (en) * 1981-11-27 1983-06-01 Hitachi Ltd Operation processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57172445A (en) * 1980-12-24 1982-10-23 Honeywell Inf Systems Information processor executing decimal multiplication using read only memory
JPS5892037A (en) * 1981-11-27 1983-06-01 Hitachi Ltd Operation processor
JPS6224816B2 (en) * 1981-11-27 1987-05-30 Hitachi Ltd

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