JPS5727360A - Accumulation instruction processing system - Google Patents

Accumulation instruction processing system

Info

Publication number
JPS5727360A
JPS5727360A JP10205280A JP10205280A JPS5727360A JP S5727360 A JPS5727360 A JP S5727360A JP 10205280 A JP10205280 A JP 10205280A JP 10205280 A JP10205280 A JP 10205280A JP S5727360 A JPS5727360 A JP S5727360A
Authority
JP
Japan
Prior art keywords
data
arithmetic
input
turns
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10205280A
Other languages
Japanese (ja)
Inventor
Masanori Mogi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10205280A priority Critical patent/JPS5727360A/en
Publication of JPS5727360A publication Critical patent/JPS5727360A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To facilitate accumulation control by increasing the number of data, by adding data, when the number of data is less than that of arithmetic stages, as many as the deficient number. CONSTITUTION:A gate 12 turns on and off an input bus for the transfer of input data, and a gate 13 also turns on and off an input 0 transferred from a 0 generator 6. A control part 14 exercises on-off control over gates 8-10, and also controls preshifting circuits 1 and 2, an arithmetic circuit 3, and a host shifting circuit 4. In an initial cycle display counter 15, the number of arithmetic stages of an arithmetic processing part is set initially, and in a vector-length counter 16, the number of data to be accumulated is set initially. Then, 0 detectors 17 and 18, when the contents of conters 15 and 16 go down to 0s, detect those and generate outputs.
JP10205280A 1980-07-25 1980-07-25 Accumulation instruction processing system Pending JPS5727360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10205280A JPS5727360A (en) 1980-07-25 1980-07-25 Accumulation instruction processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10205280A JPS5727360A (en) 1980-07-25 1980-07-25 Accumulation instruction processing system

Publications (1)

Publication Number Publication Date
JPS5727360A true JPS5727360A (en) 1982-02-13

Family

ID=14316988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10205280A Pending JPS5727360A (en) 1980-07-25 1980-07-25 Accumulation instruction processing system

Country Status (1)

Country Link
JP (1) JPS5727360A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5947643A (en) * 1982-09-13 1984-03-17 Hitachi Ltd Arithmetic processing system
JPS6072069A (en) * 1983-09-28 1985-04-24 Nec Corp Vector operation processor
JPS6267676A (en) * 1985-09-19 1987-03-27 Nec Corp Vector data processor
JPS641060A (en) * 1987-03-04 1989-01-05 Nec Corp Vector arithmetic unit
JPH0488295A (en) * 1990-07-30 1992-03-23 Matsushita Electric Works Ltd Accumulator

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5947643A (en) * 1982-09-13 1984-03-17 Hitachi Ltd Arithmetic processing system
JPH0313624B2 (en) * 1982-09-13 1991-02-22 Hitachi Ltd
JPS6072069A (en) * 1983-09-28 1985-04-24 Nec Corp Vector operation processor
JPS6248873B2 (en) * 1983-09-28 1987-10-15 Nippon Electric Co
JPS6267676A (en) * 1985-09-19 1987-03-27 Nec Corp Vector data processor
JPS641060A (en) * 1987-03-04 1989-01-05 Nec Corp Vector arithmetic unit
JPH0488295A (en) * 1990-07-30 1992-03-23 Matsushita Electric Works Ltd Accumulator

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