JPS5569849A - Multiplication control system - Google Patents
Multiplication control systemInfo
- Publication number
- JPS5569849A JPS5569849A JP14331178A JP14331178A JPS5569849A JP S5569849 A JPS5569849 A JP S5569849A JP 14331178 A JP14331178 A JP 14331178A JP 14331178 A JP14331178 A JP 14331178A JP S5569849 A JPS5569849 A JP S5569849A
- Authority
- JP
- Japan
- Prior art keywords
- multiplier
- arithmetic
- multiplicand
- circuit
- decoders
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To shorten a processing time by fixing the number of times of repetitive arithmetic of an arithmetic circuit by detecting significant digits requiring arithmetic among digits of a multiplier and multiplicand and then by alternating between the multiplier and multiplicand so that the multiplier has a less number of digits.
CONSTITUTION: A multiplier and multiplicand inputted to signal lines 11 and 12 are inputted to decoders 13 and 14 and selectors 18 and 19, and outputs of decoders 13 and 14 are compared each other by comparator 17. Next, this comparison result and the output of selector 20 connected to decoders 13 and 14 are supplied to selectors 18 and 19, where a comparison in the number of significant digits between the multiplier and multiplicand is made and the decision result is supplied to multiplier circuit 10. Further, the output of selector 20 is inputted to multiplier circuit 10 by way of substracer circuit 26, repetitive control counter 28 and zero detector 30 for repetitive arithmetic by circuit 10, thereby outputting an arithmetic output from shifter 35. In this way, arithmetic of one with less significant digits between the multiplier and multiplicand is carried out, so that a processing time can greatly be shortened.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14331178A JPS5569849A (en) | 1978-11-22 | 1978-11-22 | Multiplication control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14331178A JPS5569849A (en) | 1978-11-22 | 1978-11-22 | Multiplication control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5569849A true JPS5569849A (en) | 1980-05-26 |
Family
ID=15335807
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14331178A Pending JPS5569849A (en) | 1978-11-22 | 1978-11-22 | Multiplication control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5569849A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58129654A (en) * | 1982-01-29 | 1983-08-02 | Hitachi Ltd | Multiplication system |
JPH02206832A (en) * | 1989-02-07 | 1990-08-16 | Matsushita Electric Ind Co Ltd | Multiplier |
-
1978
- 1978-11-22 JP JP14331178A patent/JPS5569849A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58129654A (en) * | 1982-01-29 | 1983-08-02 | Hitachi Ltd | Multiplication system |
JPH02206832A (en) * | 1989-02-07 | 1990-08-16 | Matsushita Electric Ind Co Ltd | Multiplier |
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