JPS5326543A - Logical operation equipment - Google Patents
Logical operation equipmentInfo
- Publication number
- JPS5326543A JPS5326543A JP10020076A JP10020076A JPS5326543A JP S5326543 A JPS5326543 A JP S5326543A JP 10020076 A JP10020076 A JP 10020076A JP 10020076 A JP10020076 A JP 10020076A JP S5326543 A JPS5326543 A JP S5326543A
- Authority
- JP
- Japan
- Prior art keywords
- logical operation
- operation equipment
- address
- computer
- control system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE: To realize an address-assigning logical operation circuit which can improve the computing speed of a computer in a microprogram control system.
COPYRIGHT: (C)1978,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10020076A JPS5326543A (en) | 1976-08-24 | 1976-08-24 | Logical operation equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10020076A JPS5326543A (en) | 1976-08-24 | 1976-08-24 | Logical operation equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5326543A true JPS5326543A (en) | 1978-03-11 |
Family
ID=14267649
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10020076A Pending JPS5326543A (en) | 1976-08-24 | 1976-08-24 | Logical operation equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5326543A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5544650A (en) * | 1978-09-25 | 1980-03-29 | Nec Corp | Buffer memory device |
JPS57199048A (en) * | 1981-06-01 | 1982-12-06 | Ibm | Binary register mechanism |
JPS60114953A (en) * | 1983-10-31 | 1985-06-21 | サン・マイクロシステムズ・インコーポレーテツド | Computer unit employing address translation |
-
1976
- 1976-08-24 JP JP10020076A patent/JPS5326543A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5544650A (en) * | 1978-09-25 | 1980-03-29 | Nec Corp | Buffer memory device |
JPS57199048A (en) * | 1981-06-01 | 1982-12-06 | Ibm | Binary register mechanism |
JPS6143738B2 (en) * | 1981-06-01 | 1986-09-29 | Intaanashonaru Bijinesu Mashiinzu Corp | |
JPS60114953A (en) * | 1983-10-31 | 1985-06-21 | サン・マイクロシステムズ・インコーポレーテツド | Computer unit employing address translation |
JPH0584532B2 (en) * | 1983-10-31 | 1993-12-02 | Sun Microsystems Inc |
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