JPS5544650A - Buffer memory device - Google Patents
Buffer memory deviceInfo
- Publication number
- JPS5544650A JPS5544650A JP11821078A JP11821078A JPS5544650A JP S5544650 A JPS5544650 A JP S5544650A JP 11821078 A JP11821078 A JP 11821078A JP 11821078 A JP11821078 A JP 11821078A JP S5544650 A JPS5544650 A JP S5544650A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- address
- time
- storage memory
- given
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To avoid unnecessary time by installing the address storage memory of action time T, the address arithmetic circuit of process time T1 and data storage memory of action time T2 which features the parallel operation to the above-mentioned memory and circuit, along with satisfaction of T<T2<T+T1.
CONSTITUTION: Address arithmetic circuit 205 of process time T1 uses reading address 3 given from address storage memory 203 of action time T as the input and then decides whether the request address given from the CPU exists in data storage memory 204 of action time T2. Memory 204 stores the copy of main memory device MEM, and memory 203 stores the address value of the MEM containing the data. It is enough for the reading data given from memory 204 to be decided at the time point when the address operation is over. In this connection, the relation of T< T2<T+T1 is satisfied. As a result, the memory featuring a lower speed than the address storage memory is used for the buffer memory to avoid the unnecessary time.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11821078A JPS5544650A (en) | 1978-09-25 | 1978-09-25 | Buffer memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11821078A JPS5544650A (en) | 1978-09-25 | 1978-09-25 | Buffer memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5544650A true JPS5544650A (en) | 1980-03-29 |
Family
ID=14730924
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11821078A Pending JPS5544650A (en) | 1978-09-25 | 1978-09-25 | Buffer memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5544650A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03221579A (en) * | 1990-01-26 | 1991-09-30 | Arakawa Chem Ind Co Ltd | Heavy metal-trapping agent |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5222833A (en) * | 1975-08-15 | 1977-02-21 | Hitachi Ltd | Signal receiving method in the memory unit |
JPS5326543A (en) * | 1976-08-24 | 1978-03-11 | Nec Corp | Logical operation equipment |
JPS5383542A (en) * | 1976-12-29 | 1978-07-24 | Mitsubishi Electric Corp | Memory unit control system for arithmetic processor |
-
1978
- 1978-09-25 JP JP11821078A patent/JPS5544650A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5222833A (en) * | 1975-08-15 | 1977-02-21 | Hitachi Ltd | Signal receiving method in the memory unit |
JPS5326543A (en) * | 1976-08-24 | 1978-03-11 | Nec Corp | Logical operation equipment |
JPS5383542A (en) * | 1976-12-29 | 1978-07-24 | Mitsubishi Electric Corp | Memory unit control system for arithmetic processor |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03221579A (en) * | 1990-01-26 | 1991-09-30 | Arakawa Chem Ind Co Ltd | Heavy metal-trapping agent |
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