JPS5295128A - Information processing device - Google Patents
Information processing deviceInfo
- Publication number
- JPS5295128A JPS5295128A JP1144476A JP1144476A JPS5295128A JP S5295128 A JPS5295128 A JP S5295128A JP 1144476 A JP1144476 A JP 1144476A JP 1144476 A JP1144476 A JP 1144476A JP S5295128 A JPS5295128 A JP S5295128A
- Authority
- JP
- Japan
- Prior art keywords
- information processing
- processing device
- information
- cpu
- memorize
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To make it possible to memorize the information written in CPU at the address memory section of intermediate layer memory device, so that, when the previous information is erased, the processing performed by CPU which does not contain the old information, is not interrupted.
COPYRIGHT: (C)1977,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1144476A JPS5295128A (en) | 1976-02-06 | 1976-02-06 | Information processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1144476A JPS5295128A (en) | 1976-02-06 | 1976-02-06 | Information processing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5295128A true JPS5295128A (en) | 1977-08-10 |
Family
ID=11778253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1144476A Pending JPS5295128A (en) | 1976-02-06 | 1976-02-06 | Information processing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5295128A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2413718A1 (en) * | 1977-12-29 | 1979-07-27 | Fujitsu Ltd | PROCESS FOR REALIZING THE COINCIDENCE OF BUFFER MEMORIES IN A MULTIPROCESSOR COMPUTER SYSTEM |
JPS5698769A (en) * | 1979-12-14 | 1981-08-08 | Honeywell Inf Systems | Cashe memory clear operating device |
-
1976
- 1976-02-06 JP JP1144476A patent/JPS5295128A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2413718A1 (en) * | 1977-12-29 | 1979-07-27 | Fujitsu Ltd | PROCESS FOR REALIZING THE COINCIDENCE OF BUFFER MEMORIES IN A MULTIPROCESSOR COMPUTER SYSTEM |
JPS5698769A (en) * | 1979-12-14 | 1981-08-08 | Honeywell Inf Systems | Cashe memory clear operating device |
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