JPS5698769A - Cashe memory clear operating device - Google Patents

Cashe memory clear operating device

Info

Publication number
JPS5698769A
JPS5698769A JP17703780A JP17703780A JPS5698769A JP S5698769 A JPS5698769 A JP S5698769A JP 17703780 A JP17703780 A JP 17703780A JP 17703780 A JP17703780 A JP 17703780A JP S5698769 A JPS5698769 A JP S5698769A
Authority
JP
Japan
Prior art keywords
operating device
memory clear
clear operating
cashe memory
cashe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17703780A
Other languages
Japanese (ja)
Inventor
Jii Pootaa Marion
Pii Raiyan Chiyaaruzu
Eru Kingu Jieemuzu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of JPS5698769A publication Critical patent/JPS5698769A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP17703780A 1979-12-14 1980-12-15 Cashe memory clear operating device Pending JPS5698769A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10380479A 1979-12-14 1979-12-14

Publications (1)

Publication Number Publication Date
JPS5698769A true JPS5698769A (en) 1981-08-08

Family

ID=22297115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17703780A Pending JPS5698769A (en) 1979-12-14 1980-12-15 Cashe memory clear operating device

Country Status (6)

Country Link
JP (1) JPS5698769A (en)
AU (1) AU543278B2 (en)
CA (1) CA1159153A (en)
DE (1) DE3046912C2 (en)
FR (1) FR2472232B1 (en)
GB (1) GB2065941B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01115358A (en) * 1987-10-30 1989-05-08 Toru Ishiwatari Preparation of casket having kamakura carving applied thereto

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4399506A (en) * 1980-10-06 1983-08-16 International Business Machines Corporation Store-in-cache processor means for clearing main storage
US4525777A (en) * 1981-08-03 1985-06-25 Honeywell Information Systems Inc. Split-cycle cache system with SCU controlled cache clearing during cache store access period
DE3138972A1 (en) * 1981-09-30 1983-04-14 Siemens AG, 1000 Berlin und 8000 München ONCHIP MICROPROCESSORCHACHE MEMORY SYSTEM AND METHOD FOR ITS OPERATION
JPH0668735B2 (en) * 1987-02-09 1994-08-31 日本電気アイシーマイコンシステム株式会社 Cache memory
US5282201A (en) * 1987-12-22 1994-01-25 Kendall Square Research Corporation Dynamic packet routing network
US5055999A (en) * 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system
US5761413A (en) 1987-12-22 1998-06-02 Sun Microsystems, Inc. Fault containment system for multiprocessor with shared memory
US5822578A (en) * 1987-12-22 1998-10-13 Sun Microsystems, Inc. System for inserting instructions into processor instruction stream in order to perform interrupt processing
US5341483A (en) * 1987-12-22 1994-08-23 Kendall Square Research Corporation Dynamic hierarchial associative memory
US5226039A (en) * 1987-12-22 1993-07-06 Kendall Square Research Corporation Packet routing switch
US5251308A (en) * 1987-12-22 1993-10-05 Kendall Square Research Corporation Shared memory multiprocessor with data hiding and post-store
GB2216308A (en) * 1988-03-01 1989-10-04 Ardent Computer Corp Maintaining cache consistency
US5153595A (en) * 1990-03-26 1992-10-06 Geophysical Survey Systems, Inc. Range information from signal distortions
GB2256512B (en) * 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
CA2078312A1 (en) 1991-09-20 1993-03-21 Mark A. Kaufman Digital data processor with improved paging
US5724549A (en) * 1992-04-06 1998-03-03 Cyrix Corporation Cache coherency without bus master arbitration signals

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5295128A (en) * 1976-02-06 1977-08-10 Hitachi Ltd Information processing device
JPS5361236A (en) * 1976-11-12 1978-06-01 Fujitsu Ltd Memory access control system

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771137A (en) * 1971-09-10 1973-11-06 Ibm Memory control in a multipurpose system utilizing a broadcast
US3845474A (en) * 1973-11-05 1974-10-29 Honeywell Inf Systems Cache store clearing operation for multiprocessor mode
JPS5440182B2 (en) * 1974-02-26 1979-12-01
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging
US4020466A (en) * 1974-07-05 1977-04-26 Ibm Corporation Memory hierarchy system with journaling and copy back
US4136386A (en) * 1977-10-06 1979-01-23 International Business Machines Corporation Backing store access coordination in a multi-processor system
DE2947115A1 (en) * 1978-12-11 1980-06-26 Honeywell Inf Systems DELETING ARRANGEMENT FOR A CACHE MEMORY OF A PROCESSOR IN A MULTIPROCESSOR SYSTEM

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5295128A (en) * 1976-02-06 1977-08-10 Hitachi Ltd Information processing device
JPS5361236A (en) * 1976-11-12 1978-06-01 Fujitsu Ltd Memory access control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01115358A (en) * 1987-10-30 1989-05-08 Toru Ishiwatari Preparation of casket having kamakura carving applied thereto

Also Published As

Publication number Publication date
AU6532480A (en) 1981-06-18
DE3046912A1 (en) 1981-09-03
GB2065941A (en) 1981-07-01
AU543278B2 (en) 1985-04-18
GB2065941B (en) 1984-02-29
DE3046912C2 (en) 1994-05-11
FR2472232A1 (en) 1981-06-26
FR2472232B1 (en) 1988-04-22
CA1159153A (en) 1983-12-20

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