GB2065941A

GB2065941A - Cache store system

Info

Publication number: GB2065941A
Application number: GB8039948A
Authority: GB
Original assignee: Honeywell Information Systems Italia SpA; Honeywell Information Systems Inc
Current assignee: Bull HN Information Systems Italia SpA; Bull HN Information Systems Inc
Priority date: 1979-12-14
Filing date: 1980-12-12
Publication date: 1981-07-01
Also published as: CA1159153A; DE3046912C2; DE3046912A1; GB2065941B; FR2472232A1; JPS5698769A; AU543278B2; FR2472232B1; AU6532480A

Abstract

A cache clearing apparatus for a multiprocessor data processing system having a cache unit 41-43 and a duplicate directory 73-75 associated with each processor 37-39. The duplicate directory, which reflects the contents of the cache directory within its associated cache unit, and the cache directory are connected through a system controller unit 53, 58, 59. Commands affecting information segments within the main memory 50 are transferred by the system controller unit to each of the duplicate directories to determine if the information segment affected is stored in the cache memory of its associated cache memory. If the information segment is stored therein the duplicate directory issues a clear command through the system controller to clear the information segment from the associated cache unit. <IMAGE>

Description

SPECIFICATION Cache memory system This invention relates to data processing systems and, more particularly, to data processing systems having multiple processors with each processor having a cache connected thereto and a duplicate directory associated with a system controller.

A cache is a small, generally high speed memory store unit (cache memory) and a directory for locating the information within the cache memory. The cache memory is generally of a higher order of speed than the main memory.

Thus, if the information is stored in the cache memory quicker access by the processor to the required information is possible. Further, the cache memory is generally a small fraction of the size of the main memory. Operands and instructions, hereinafter generically referred to as information segments or data, are either fetched from the main memory and stored into the cache memory or they are loaded directly from the central processing unit (CPU). When the CPU requires information segments the cache memory is accessed first. If the information segments are not present in the cache memory, then they are obtained by accessing the main memory. The accessed information segments provided by the memory and transferred to the processor can be stored into the cache as they are passed through the CPU.

Generally it is desirable that the main memory contain all of the information segments and that the cache memory only reflects what is in the main memory. If a peripheral device requests and has transferred to it the contents of a portion of the memory, and further clears the information segments as they are provided from the main memory, it is possible that the cache of one or more of the processors could contain data which is no longer present in the main memory. Further, one of the processors may write an information segment into a particular storage location within the main memory. The cache of another processor can contain the information segment which has just been replaced by the first processor.

Therefore, it is possible that if the processor accesses that particular information segment present in its cache memory, it could act upon data which is no longer identical with the information segment in the main memory. It is therefore necessary to provide some form of cache clearing operation.

One type of cache clearing operation is to clear the entire cache of all the processors anytime data is written into the main memory or cleared by a peripheral device. However, in the usual case, the majority of the information segments stored within the cache are not utilized as output to the peripheral device and it is likely that information segments just cleared will have to be retrieved again fron the main memory.

Many data processing systems utilize segmentation and paging of the memory.

Segmentation is usually divided into smaller sections referred to as pages. The pages correspond to particular storage locations within the cache memory. Thus, it is possible to construct a device which provides selected clearing of only certain memory locations, i.e., those associated with particular page, if that particular page is effected by an input/output operation or by another processor. Although in such a device the entire cache memory is not cleared, the fact remains that useful data within the cache memory can be erased if that data relates to the page which is affected. It would therefore be necessary to access those information segments from the main memory under subsequent operations of the CPU.

Neither of these prior constructions shows a selective cache clearing utilizing a duplicate directory which communicates with the cache directory through the system controller.

It is an advantage of this invention to provide a plurality of duplicate directories operating through a system controller which ensures that none of the caches contain different information segments for certain memory locations than the corresponding information to those certain memory locations stored within the cache memory.

It is a further advantage of this invention to provide a plurality of duplicate directories which respond to information being used and cleared by peripheral devices through the system controller unit to ensure that if a location within the main memory is cleared by the peripheral device or over-written, that the cache memory of the various central processing units contain only information segments which are currently stored within the main memory.

A multiprocessor data processing system in accordance with the invention will now be described, by way of example, with reference to the drawings, in which: Figure 1 is a block diagram showing the basic architecture of a data processing system; Figure 2 is a block diagram of a multiprocessor of a processing system including cache units associated with each processor and a plurality of duplicate directories; Figure 3 is a block diagram of a cache unit shown in Figure 2; Figure 4 is a block diagram of a duplicate directory shown in Figure 2; and Figure 5 is a logic diagram of the operation of the duplicate directories shown in Figure 2.

Introductory Summary The present system involves the cache clearing apparatus of a multiprocessor data processing system having a plurality of duplicate directories.

Each duplicate directory is connected through a system controller unit to the cache of its corresponding processor. Each cache has a cache directory and a cache memory.

For the purposes of utilization of the address of a particular information segment within the main memory as an address tag for the cache, the main memory address is divided into an upper and lower portion. The lower portion comprises the least significant bits of the address and the upper portion the most significant bits of the address.

The lower portion is utilized to address a set of address tags within the cache directory. The cache directory outputs all of the address tags within the set in parallel to a comparator. The address tags are compared with the upper portion of the address to determine if the information segment sought is stored within the cache memory. If there is a match between the address tag and the upper portion of the main memory address, the particular information segment within the cache memory corresponding to the address tag of the set is selected. This is accomplished by assigning each address tag of the directory a level which corresponds to a level of the cache. For example, if the directory may be organized such that there are eight levels, i.e., eight address tags which are addressed by the lower portion of the main memory address. The cache must correspondingly have eight levels.The comparator receives the eight address tags so that it is aware of the level of each address tag. If a match between one of the address tags and the upper portion of the main memory address is found, the comparator outputs a signal indicating to the cache which of its eight levels should be selected as output.

The address tags are stored into the directory by having the lower portion of the main memory address selected as the address for the directory and upper portion of the main memory address present at the write inputs of the cache directory.

The particular level is selected by a round robin counter (or any other standard method). Also associated with each address tag is a bit which indicates the full/empty status of the corresponding storage location within the cache memory. If the full/empty bit is set, this indicates that the corresponding storage location within the cache memory contains a valid information segment which can be utilized by the CPU. If the full/empty bit is not set, the comparator does not indicate a match and does not select one of the levels within the cache memory even though the tag address for that level is identical with the upper portion of the main memory address. Thus, it is unnecessary to clear the entire address tag or utilize some other procedure to clear the cache memory.The full/empty bit of cache directory is set when an information segment is written into the cache and the upper portion of the main memory address is written into the directory as an address tag along with the assigned level. As shown herein, the upper portion of the main memory address can only be written into the directory from the CPU. However, the full/empty bit can be accessed through a block clear instruction containing a lower portion of the address from the system controller unit. The cache is connected through the system controller unit to the main memory and a duplicate directory. Each cache of the multiprocessor data processing system has one duplicate directory associated therewith. Each duplicate directory has storage locations which correspond to the storage locations within the cache directory.The duplicate directory is capable of storing address tags and levels, and the associated full/empty bits. The system controller unit or units are connected to each of the duplicate directories.

The duplicate directory receives the indications that a particular address tag has been written into the directory and the full/empty bit set indicating that the information segment within the cache memory is valid. The duplicate directory responds to this indication by storing the address tag at the same level and by setting its full/empty bit.

If, for example, another processor writes into a particular main memory location, the system controller associated therewith sends a signal to the other duplicate directory indicating the main address which is affected. Each duplicate directory examines its contents to determine if that particular address tag formed by the upper portion of the main memory address, as addressed into the duplicate directory by the lower portion of the main memory address, is present therein. If one of the address tags is determined to be the upper portion of the main memory address by comparison and the full/empty bit is set, the duplicate directory resets the full/empty bit to indicate that the information segment contained in the cache at that address is no longer valid. The directory then sends a clear signal to the directory of its associated cache.The clear signal contains the level and the lower portion of the main memory address. The level sent, of course, is the level in which the address tag which corresponded to the upper portion of the main memory address was located. The clear signal also contains instructions to the cache that the full/empty bit of the address level must be reset to indicate that the information segment located in the cache is no longer valid.

The system control unit is also connected to various peripheral units which both transfer information segments to be stored in the main memory and receive information segments from the main memory for utilization by the peripheral devices. Peripheral devices are instructed through the system controller unit by one of the CPUs to read and clear a portion of the memory. Thus, the peripheral device through the system controller unit requests information segments from certain addresses within the main memory and clears the information segments contained therein. The system controller unit, when a particular address within the main memory no longer contains a valid information segment because it has been cleared by the peripheral, sends the address of that cleared information segment and an indication that the address has been cleared to each of the duplicate directories. The duplicate directories then utilize the lower portion of the main memory address to access the appropriate set of address tags within the duplicate directory. The upper portion of the main memory address is compared with the address tags. If one of the address tags is identical with the upper portion of the main memory address and the full/empty bit is set (i.e., the cache contains a valid information segment), the full/empty bit within the directory associated with the particular address tag is reset to indicate that the cache memory does not contain a valid information segment. A clear signal is then sent to the cache and the full/empty bit of the cache directory is also reset as discussed above.

Detailed Description Figure 1 shows a CPU 10 connected through multiline channel 12 to a cache 14. Cache 14 is connected through multiline channel 16 to a system controller unit 18. The system controller unit 18 is connected through multiline channel 20 to a main memory 22. Peripheral devices 24 and 25 are connected through multiline channels 27 and 28 respectively, to system controller unit 18.

The central processing unit sends requests for information segments from the main memory 22.

The central processing unit can also issue commands through multiline channel 12 that certain information segments be stored into the main memory 22. The requests for information to be read and commands to write pass through the cache 14. The read command generally initiates a search through the cache directory (not shown) utilizing the address which is provided by the central processing unit to a particular storage location within the main memory, to determine if that information segment is present in the cache memory. If the information segment is present in the cache, the information segment is read from the cache memory and sent to the central processing unit through multiline channel 12. The request for the information segment from the main memory 22 is aborted.If the information segment is not present within the cache memory, as determined from the main memory address, the read request is passed through multiline channel 16 to the system controller 18 and through multiline channel 20 to main memory 22. The stored information segment is read utilizing the address provided by the central processing unit.

The information segment read passes back through multiline channel 20, system controller 18, multiline channel 16, cache 14 and multiline channel 12 to the central processing unit 10.

Generally the information segments from the main memory are stored into the cache memory within cache 14 so that if the central processing unit desires the utilization of those information segments during subsequent operations they are available within the cache.

During a write command the information segments to be written into the main memory 22 pass through multiline channel 12, cache 14, channel 16, system controller unit 18, and channel 20. The central processing unit can provide that the information segments written into the main memory are also written into the cache memory (not shown) within cache 14. It should be noted that all of the information segments present within the cache memory are in traditional architecture also located within the main memory 22.

Peripheral devices 24 and 25 are capable of either receiving information segments from system controller 18 or providing information segments thereto or both. For example, if peripheral device 24 is providing information segments to be written in main memory 22, the information segments proceed through channel 27, system controller 18, and channel 20. If any of the information segments within main memory 22 are over written by information segments from peripheral 24, or if there is any possibility that this may occur, the cache memory within cache 14 must be cleared. At the very least, the information segments overwritten must be cleared. As discussed above in the connection with the prior art, this has been accomplished by clearing the entire cache memory during a read operation from a peripheral device.

If, for example, peripheral device 25 is to read information segments from main memory 22 and cause those memory segments to be cleared, the information segments cleared from the main memory which are present within the cache memory must also be cleared. In the past, as discussed above, the cache memory within cache 14 was completely cleared and not just those information segments which were removed from the main memory that are present therein. It should be noted that one technique to clear the cache memory is to merely clear a full/empty bit located within the directory associated with the cache memory.

With particular reference to Figure 2, a multiprocessor data processing system 34 utilizing the present system is shown. Data processing system 34 is shown with central processing units (CPU) 37 to 39, each of which is -connected to a respective one of cache units 41 to 43 through multiline channels 45, 47 and 48 respectively.

Through multiline channels 45, 47 and 48, the central processing units request information segments from the main memory 50 and command that certain information segments provided by the central processing unit be written into the main memory 50. The operation of the cache units 41 to 43 will be discussed in detail in conjunction with Figure 3. Cache unit 41 is connected through multiline channel 53 to a system controller unit 55. System controller units 58 and 59 are connected through multiline channels 61 and 62, respectively, to cache units 42 and 43, respectively. Although not shown in Figure 2, the system controller units 55, 58 and 59 are also connected to peripheral devices (not shown) such as those peripheral devices 24 and 25, as shown in Figure 1.

System controllers 55, 58 and 59 can be one system controller adapted to service one or more central processing units. If more than one system controller is utilized, then each of the system controller units must be in electrical communication with all the remaining system controller units so that their activities can be properly co-ordinated, as shown by multiline channels 64, 65 and 67. It should be noted that all of the channels shown in Figure 2 provide twoway communication for the units between which they are connected. System controllers 55, 58 and 59 are connected through multiline channels 69, 70, and 71, respectively, to main memory 50.

Each cache unit 41 to 43 has one duplicate directory, 73 to 75 respectively, associated therewith. Each of the three duplicate directories 73 to 75 is connected through three respective multiline channels to each of the three system controllers 55, 58, and 59 by multiline channels 77, 79, 80, 82, 84, 85, 88, 89, and 92 as shown.

The central processing units 37, 38 and 39 can request an information segment from memory 50 by providing an address to the particular memory location containing the desired information segments and a read command. The central processing units 37, 38, and 39 can also write information segment into main memory 50 by commanding the system controller unit 55, 58, and 59, respectively and providing the address into which the particular information segment is to be written and the information segment. For example, central processing unit 37 requests information segments located at a particular address within the main memory through multiline channel 45, cache unit 41, channel 53, system controller 55, and channel 69.This read command indicates that the information segment at a particular address within the command is to be transferred to the central processing unit 37. The main memory 50 locates the information segment utilizing the address included with the read command and provides the information segments through channel 69, system controller unit 55, channel 53, cache 41, and channel 45 to central processing unit 37. Read commands can also be issued by the peripherals connected to the system controller units 55, 58 and 59. The read commands can also clear information segments from the main memory after the information segments are transferred through the applicable system controller unit.

When the central processing unit 37 requests a particular information segment, the request first goes to cache unit 41 through channel 45. Cache unit 41 normally determines if the requested information segment is stored within its memory 110 (Figure 3). If the information segment is present within the cache memory, the read operation to the main memory is aborted. If the information segment is not contained within the cache memory, the operation continues as discussed above and the information segment is obtained from the main memory 50. As specified by the central processing unit 37, when the particular information segment requested from the main memory 50 is transferred from the system controller 55 to the cache unit 41, the information segment is both passed on to central processing unit 37 and stored into the cache memory 110 (Figure 3) within the cache unit 41.

When central processing unit (CPU) 37 issues a write command and provides the address of the storage location within main memory 50 into which the information segment, provided by central processing unit 37, is to be written, the write command can if central processing unit 37 so indicates cause cache unit 41 to write the information segment into cache memory 110 (Figure 3). The write command is then passed to system controller 55 and ultimately to the main memory 50 to be written into the storage location addressed.

Duplicate directory 73 which is associated with cache unit 41 maintains a record of all the storage locations of main memory 50 which have their contents also stored in the cache memory of cache unit 41. Duplicate directory 73 determines whether or not there is a match between the storage location currently being addressed and a storage location indicated as having its information segment also located in cache memory 110 (Figure 3) of cache unit 41. The particular storage and retrieval method utilized by the duplicate directory and the cache unit for determining whether or not the particular main memory storage location addressed has its information segment located in the cache memory is similar.

The duplicate directory 73 also receives inputs from the other system controller units 58 and 59 for determining if any of the operations of the central processing unit or any peripherals passing through the system controller units affect any of the storage locations within main memory which also have their information segments also stored within cache unit 41. For example, if the system controller unit 58 receives a write command from central processing unit 38 to write into a certain memory location within the main memory, duplicate directories 73 and 75 are notified through channels 79 and 89. The duplicate directories 73 and 75 check their contents to determine if the associated cache units 41 and 43 respectively contain the information segment present in that particular storage location.If duplicate directory 73 determines that the information segment is located within the cache memory 110 of cache unit 41, a clear command is initiated by the duplicate directory 73 through channel 77. The system controller 55 passes the command through channel 53 to cache unit 41 and that particular information segment is cleared from the cache memory of the cache unit. If duplicate directory 75 determines that cache unit 43 contains the information segment of that particular storage location it also issues a clear command on channel 92 which is passed through system controller unit 59 to the cache unit 43. The particular information segment is cleared from the cache memory (not shown) of cache unit 43.

A similar sequence occurs if the system controller unit 58, as commanded by central processing unit 83, allows a peripheral to read and clear main memory storage locations. Duplicate directories 73, 74, and 75 check each address of the storage locations to determine whether or not cache units 41,42 and 43, respectively, contain the information segment present in that particular main memory storage location. If duplicate directory 73 determines that the cache memory 110 of cache unit 41 contains the information segment present in that particular main memory storage location, the duplicate directory issues the clear command as discussed above.Duplicate directories 74 and 75 also issue clear commands if it determines that the associated cache memory (not shown) within cache units 42 and 43 contain the information segment in that particular memory storage location of the main memory 50.

Cache unit 41 of Figure 2 is shown in more detail in Figure 3; cache units 42 and 43 are similar. As shown in Figure 2, the input lines 112 and the output lines 114 of channel 45 are shown separately. The standard timing and other logic command functions in an apparatus of this type are utilized throughout. Therefore, lines other than 112 and 114 will be present within channel 45.

The same is true of the other channels, which will be discussed in more detail in connection with Figures 3 and 4.

Input lines 112 feed data switches 11 8, 11 9, and 120, registers 122 to 124, and comparator 126. Data switch 11 9 receives only the lower portion of the main memory address and provides the address for cache directory 129. Cache directory 129 is a random access memory which is organized on an associative addressing by levels system. Data switch 11 9 feeds, via the multiline channel 132, a data switch 135, directory 129, and register 137. Register 137 feeds via channel 140 a data switch 119.

Data switch 135 feeds, via multiline channel 142, an address register 143. Address register 143 provides the necessary addressing to cache memory 110 through multiline channel 144. The data to be written into cache memory 110 is provided through multiline channel 146 from data switch 11 8. Comparator 126 feeds, via channel 148, data switch 151. Data switch 151 also receives the outputs of cache memory 110 through a plurality of channels 155. Data switch 151 feeds register 158 through multiline channel 160. Register 158 feeds, via multiline channel 162, a data switch 164 which feeds the output lines 114 to CPU 37 (Figure 2).

If data is to be written into the cache memory from CPU 37 the command comes through input lines 112. The write command will contain the entire main memory storage location address for the particular information segment to be written into the cache memory. The lower portion of the address (bits 24-30) are applied through data switch 11 9 to cache directory 129. The upper portion of the address is applied to comparator 126 and cache memory 110. The information segment to be written into cache memory 110 is applied from input lines 11 2 through data switch 118 and channel 146 to cache memory 110.The address for the location within the cache memory where the information segment is to be stored is provided by the lower portion of the main memory address through channel 132, data switch 135, and channel 142 as stored into register 143.

Cache memory 110 is such that the address provided through channel 144 from register 143 selects a set of eight storage locations for the information segment. The particular one of the eight storage locations (hereinafter referred to as levels) is provided by a round robin counter (not shown) within control unit 167. When the lower portion of the address is applied to the cache directory 129, a set of eight different address tags in eight storage locations within the cache directory are provided as outputs to comparator 126. Comparator 126 determines if any of the set of eight different address tags provided is identical with the upper portion of the main memory (consisting of the bits 10-23).

During a standard read operation, the command from CPU 37 enters the cache 41 and the data switch 11 9 is commanded by control unit 167 to apply the lower portion of the address to cache directory 129 and data switch 135. Data switch 135 is commanded to select the output of data switch 132 by control unit 167. The lower portion of the main memory address is stored into register 143. The output of cache memory 110 is one of eight information segments which pass through channels 155 and are selectable by switch 151.

The selection of one of the eight information segments of the output of switch 151 is made by comparator 126. When the lower portion of the main memory address is applied from switch 11 9 to the directory 129, the output of the cache directory to comparator 126 is eight address tags, which are the upper portion of the main memory address for the eight corresponding information segments stored into the cache memory 110. A comparison is made by comparator 126 between the upper portion of the main memory address from input lines 11 2 and each of the address tags provided by cache directory 129. If any of the address tags match the upper portion of the main memory address the comparator 126 indicates which level is associated with the address tag.The level output to switch 151 causes the switch to select that level, and the correct information segment is loaded into register 158 to be passed through data switch 164 to the CPU 37 (Figure 2). Data switch 164 is controlled by control unit 167: In a particular form of the cache directory, the level which the information segment within the cache memory 110 occupies is stored along with the upper portion of the main memory address (or address tag). Also associated with the address tag (or upper portion of the main memory address) are full/empty bits which indicate whether the particular address tag corresponds to a valid information segment within the cache memory 110.The commands and the address for the proper storage location within the main memory are not only applied to data switch 11 9 and comparator 126, but also to a plurality of transient storage registers shown in register 123. Control unit 167 provides the necessary control signals to register 123. It has been found useful to have in certain applications the capability to store four separate read requests. Each register is adapted not only to store the command segment of the read request but also the address within the main memory and the level assigned within cache memory 110 where the information segment read from the main memory is to be stored if the information segment is not contained in the cache memory.If comparator 126 determines that the information segment is already present in cache memory 110, the read operation is aborted and that particular read request is removed from register 123. Under certain conditions read requests are entered into register 123 while the cache memory in the cache directory performs other functions.

It is sometimes desirable that the lower portion of the address stored within register 123 be applied to data switch 135 through multiline channel 1 78. The lower portion of the main memory address which is applied through data switch 135 and stored into register 143 from register 123 is utilized to provide the address for cache memory 110 as the data is read back from the main memory through the system controller unit (to be discussed in detail later). The output of register 123 is also applied to a comparator 181 and a data switch 182. Data switch 182, which is controlled by control unit 167, has its output applied through output lines 186 of channel 53 to the system controller unit 55 (Fig. 2). The output of data switch 182 is also applied to data switch 118 through multiline channel 188.

Comparator 180 compares the output of data switch 120 with the contents of register 123 to determine if any of the read requests are in register 123 are present again on line 112 or if a clear command (discussed in detail later, register 210) is received from the system controller unit.

The output of comparator 182 to line 190 prevents comparator 126 from providing an output to prevent an information segment which is to be cleared from being transferred to the CPU 37. Line 190 can also be connected to control unit 167.

Write commands from the CPU are stored into register 124. Control unit 167 can provide the proper control signals for loading the write command into register 124. The output of register 124 is connected to data switch 182 through multiline channel 197. The address of the information segment which is to be stored into the main memory can pass through data switches 119 and 135 and be entered into register 143.

The information segments which are loaded can pass through data switch 182 from register 124 and through channel 188 and data switch 118 for entry into cache memory 110. At the same time, the lower portion of the main memory address becomes an address tag and is loaded into cache directory 129 at the level determined by the round robin counter (not shown). The same level is simultaneously provided to the cache memory 110. The level is entered into the cache directory along with the address tag and the full/empty bit is set to indicate full.

Under certain conditions it is necessary that the lower portion of the main memory address be stored temporarily prior to utilization of the cache directory in the cache memory. In this event the lower portion of the main memory address is loaded into register 137 and the output of data switch 11 9 becomes the output of register 137 at the appropriate time.

The input lines 199 from system controller unit 55, which are a portion of the lines comprising channel 53, are connected to a register 204. The output of register 204 is connected through channel 206 to register 210 and data switches 118 and 164. Thus, data switch 164 can select the output of either register 1 58 or register 204.

Register 210 stores clear commands from the system controller unit 55. Up to four such commands can be stored into register 210. The clear commands are then applied through multiline channel 212 to data switches 120 and 11 9. These clear commands assume a priority as controlled by the control unit 1 67 over the ordinary operations of the cache unit 41. The lower portion of the main memory address is provided through data switch 11 9 to the cache directory. The full/empty bit of the appropriate address tag within cache directory 129 is set to indicate that the cache memory is empty (i.e., the information segment contained in that particular location within the cache memory no longer represents a valid information segment).As a part of the command stored within register 210, the level of the address tag is provided to cache directory 129 (through lines not shown) and can be routed through the round robin counter to provide the necessary information to locate which of the eight address tags as addressed by the lower portion of the main memory address provided from register 210, is to have its full/empty bit reset. In an ordinary read command the information segment to be written into the cache memory is provided through channel 206 to cache memory 110 through data switch 118 and the lower portion of the main memory address provided to register 143 either from register 137 or from register 123. The information segment would be written in the cache memory, after it is read from the main memory, when it was not located within the cache memory and the read operation not aborted.

Duplicate directory 73 (Figure 2) is shown in detail in Figure 4; duplicate directories 74 and 75 are similar. The multiline channel 77 as shown in Figure 4 comprises input lines 220 and output lines 222. The input lines 220 feed registers 225 and 226. The read and write commands from central processing unit 37 (Figure 2), transferred through cache unit 41 and system controller unit 55, enter the duplicate directory from the system controller unit 55 through input lines 220. These commands are also passed to the main memory through channel 69 (Figure 2). Register 226 provides as an output the command and the address portion thereof to data switch 228.

Directory logic unit 230 examines the command within register 226 through multiline channel 232. The command indicates that information has been written into the cache memory or will be written into the cache memory upon having the information read from memory 50 (Figure 2). In the event that the command indicates that there has been or will be a change in the directory 129, the directory 230 issues a set or reset signal through line 235 to the duplicate directory memory 237. Logic unit 230 also operates the data switch 228 and data switch 239 through lines 241 and 242, respectively. If necessary the read and write commands from the central processing unit can be stored into register 225, which can store more than one command.

Read/clear signals from the peripherals through system controller unit 55 can also be stored into register 225.

The read and write commands and clear commands from system controller units 58 and 59 are connected through channels 79 and 80, respectively, to registers 244 and 245, respectively, which can store more than one command. Registers 244 and 245 are connected through multiline channels 247 and 249 to switch 239 as shown, and register 225 also feeds data switch 239 through multiline channel 251. Data switch 239 feeds, via multiline channel 253, a register 255 which feeds data switch 228 through multiline channel 257. Thus, any commands from the system controller unit 55 (Figure 2) can be loaded into register 226 if immediate action is required and that register selected as the output of data switch 228. Alternatively the commands can pass through register 225 and be selected by the data switch 239 feeding register 255.

The control unit 230 can select register 255 by data switch 228, which feeds, via multiline channel 259, a register 261, duplicate directory memory 237, and a comparator 264. Only the address of the main memory storage location affected by the command is passed to register 261 to be loaded therein. The lower portion of the memory address is utilized through channel 266 as the address for the duplicate directory memory 237. The upper portion of the main memory address is applied to the duplicate directory memory 237 through multiline channel 268. The upper portion of the main memory address and the level are applied to the duplicate directory memory for storage therein. The full/empty bit of an address tag is set or reset by logic unit 230 through line 235. The upper portion of the main memory address is also applied to comparator 264.If the duplicate directory memory is being read to determine if a particular address tag is identical to the upper portion of the main memory address on channel 259, eight address tags are applied through multiline channel 270 to comparator 264. Comparator 264 determines if any of the address tags represent the upper portion of the main memory address. If any of the address tags are identical with the upper portion of the main memory address, the level associated with that address tag becomes the output of comparator 264 through multiline channel 272 as an input to register 261. The function of the duplicate directory 73 of Figure 4 is discussed in detail in connection with Figure 5. However, a brief example of the operation should be helpful at this point.

Central processing unit 38 generates a write command to a particular address in the main memory. This command passes through cache unit 42 and enters system controller unit 58.

System controller unit 58 sends the address of the command and its nature through multiline channel 79 and the command is stored into register 244.

At some point the contents of register 244 which represent this write command are loaded into register 255 through switch 239 under the control of logic unit 230. Register 255 is selected as the output of data switch 228 and the address is applied to the duplicate directory memory as discussed above. Assuming that the cache memory 110 contains the information segment which was present prior to this write command, the duplicate directory memory will contain the address tag for that particular memory location and comparator 270 will output the level of that address tag.

It should be noted that comparator 264 also determines if the full/empty bit associated with the address tag which is identical to the upper portion of the main memory address is set. If the full/empty bit is not set the comparator 264 does not send the level to register 261. A clear command is generated by register 261 under the control of the logic unit 230. This clear command contains the necessary code which is recognized as a clear command by cache unit 41 along with the lower portion of the main memory address from register 55 provided through data switch 228 and the level determined by comparator 264.

This clear command is passed to system controller unit 55 through output lines 222. System controller unit 55 (Figure 2) passes the clear command to cache unit 41 through input lines 199. The clear command is recognized by the control unit 167 and is loaded into register 210.

The lower portion of the main memory address is applied to cache directory 129 through switch 11 9 from register 210. The level which is to be cleared is supplied through the round robin counter (not shown) for example, and the full/empty bit of the appropriate one of the eight address tags addressed by the lower portion of the main memory address has its full/empty bit reset.

The full/empty bit being reset indicates that the information segment contained within cache memory 110 which is associated with particular address tag is no longer valid.

The operation of duplicate directory 73 and cache unit 41 will be discussed in detail in connection with the logic flow diagram of Figure 5. The logic after initialization enters into logic state 277. The logic passes from state 277 to logic state 279, where a test is made to determine if a command has been received by registers 225, 226, 244, or 245 (Figure 4). If a command has not been received, the logic cycles through path 280 and re-enters state 277. If a command is received the logic enters state 281, where a test is made of whether the command received originated with the associated central processing unit 37. The commands present in registers 244 and 245 are from system controller units 58 and 59, respectively. The commands present in registers 225 and 226 are from system controller unit 55.If the command received is from CPU 37 through system controller unit 55, the logic passes through path 284 to state 286. However, if the determination is made in state 281 that the command originated with central processing units 38 or 39 or one of the peripheral units connected to any of the system controller units 55, 58 or 59, the logic proceeds through path 289 to state 291.

Assuming that the command originated with either central processing units 38 or 39, or from any of the peripheral devices connected to the system controller units 55, 58 or 59 and the logic is currently within state 291, test is made of whether the particular command is a read command. If the command is a read command the logic proceeds through path 294 to state 296, in which the requested data is sent from the main memory 50 (Figure 2) to the appropriate system controller unit and from there to the requesting peripheral device or central processing unit. The duplicate directory 73 takes no action. If the received command is not a read command, the logic passes from state 291 to state 298, in which the logic tests whether this particular command is a read/clear command.If it is a read/clear command the logic passes from state 298 to state 304, in which the address of the requested information is applied to the duplicate directory memory 237 (Figure 4). The contents of the duplicate directory memories (not shown) provided in duplicate directories 74 and 75 are also examined.

The logic then proceeds from step 304 to state 307, in which a test is made of whether or not the comparators such as comparator 264 (Figure 4) have identified any of the address tags which were addressed by the lower portion of the main memory address as matching the upper portion of the main memory address. If the comparator 264, for example, does not locate the address tag within the duplicate directory memory, the logic proceeds through path 310 to step 296, in which the requested information segment is passed from the main memory to the requesting system controller unit and on to either the requesting central processing unit or the requesting peripheral device.If in state 307 a comparator finds that a match exists between the upper portion of the main memory address and one of the address tags which were addressed by the lower portion of the main memory address, the logic proceeds from state 307 to 312, in which the full/empty bit of the address tag which matches the upper portion of the main memory address is reset to indicate that the corresponding location within the cache memory does not contain a valid information segment.

The level of the address tag which corresponded to the upper portion of the main memory address is sent through channel 272 and enters register 261. Register 261 under the command of logic unit 230 generates a clear command. The address for the lower portion of the main memory address is obtained from register 255 and loaded into register 261. The clear command is then transferred through output lines 222 and input line 199(Figure 3), and enters register 204. The clear command in then loaded into register 210 and the full/empty bit addressed by the lower portion of the main memory address and at the level included within the command, as provided by the command, has its full/empty bit reset indicating that the cache memory 110 location which corresponds thereto does not contain a valid information segment.The logic then proceeds from state 312 to state 296 and the data is sent from the main memory 50 (Figure 2) to the requesting peripheral device or central processing unit.

If the command examined in state 298 is not a read/clear command, the logic goes to state 318 through path 316. This implies the command is a write command to write an information segment into the main memory 50. In state 318, the duplicate directories 73, 74 and 75 are examined to determine if their associated cache memories containing the information segment which has the main memory address provided by the write command if the command was issued by a peripheral device. Thus the lower portion of the main memory address is applied to the duplicate directory memories within duplicate directories 73, 74 and 75. The logic then proceeds from state 31 8 to state 320.If the write command is from CPU 42 or 43, the address tag and level are written in to the duplicate directory memories of duplicate directories 74 or 75 respectively in state 31 8 if any entry was made into the associated cache.

In state 320, the logic examines the outputs of the comparators within the duplicate directories 73, 74 and 75 (the comparator in duplicate directory 73 being comparator 264) to determine if the duplicate directory memories contain an address tag which indicates that the associated cache units 41,42 and 43, respectively, contain an information segment which corresponds to that main memory address. If an address tag was written into a duplicate directory memory in step 318, the associated comparator is not examined.

If it is determined that none of the address tags indicate that the cache memories contain that particular information segment then the logic proceeds through path 322 to state 324. If it is determined that one or more duplicate directory memories within duplicate directories,73,74, or 75 contains an address tag indicating that the associated cache memory has the information segment affected by the write command, the logic proceeds from state 320 to state 326, in which the full/empty bit within the duplicate directory memory is reset for the particular address tag and a clear command is sent to the cache unit having that particular information segment stored in its cache memory. Of course, if the duplicate directory memory was written into in state 318, the full/empty bit is not reset in state 326.

From state 326, the logic proceeds through path 328 to state 324, in which the write operation is completed in main memory 50 and an operation complete signal is sent to the requesting system controller unit by its associated duplicate directory and by the main memory 50. The operation complete signal can be conveyed through the system controller 55 and cache unit 41 to the central processing unit 37 is desired.

The logic then proceeds from state 324 and reenters state 277.

Assuming while the logic was in state 281 that the command received was from the central processing unit 37 and the logic flows through path 284 to state 286, the logic proceeds as follows. In state 286 a test is made to determine if the command is a read command. If the command is not a read command the logic proceeds through path 330 and enters into state 332, in which the read command is again examined to determine if the command represents a read/clear operation. If the command does not represent a read/clear command, the logic proceeds through path 334 to step 336. Under these conditions it follows that the command is a write command. The upper portion of the main memory address is written into the proper location within the duplicate directory memory 237 (Figure 4) as an address tag utilizing the lower portion of the main memory address on channel 266.The write command includes the level to be associated with the address tags. The full/empty bit is set.

The logic then proceeds from state 336 to state 338, in which the other duplicate directory memories are examined by the duplicate directories 74 and 75 to determine if an address tag exists which corresponds to the upper portion of the main memory address. The address tags examined represent the eight address tags which are transferred to the comparator from the duplicate directory memory when addressed by the lower portion of the main memory address.

The logic then proceeds from state 338 to state 340, in which a test is made to determine if the comparators within duplicate directories 74 and 75 have identified any of the address tags in the duplicate directory memory as identical to the upper portion of the main memory address.

If none of them show a correspondence, i.e., none of the address tags is identical with the upper portion of the main memory address, the logic proceeds through path 342 to state 324 and proceeds as discussed above. if the comparators within duplicate directories 74 and 75 determine that an address tag is identical with the upper portion of the main memory address, the logic proceeds from state 340 and state 344, in which (as in step 326) the clear commands with the lower portion of the main memory address and the level provided by the comparator are sent to the appropriate CPU 38 or 39. The logic then proceeds through the path 346 and enters step 324.

If while the logic is in state 332 it is determined that this is a read/clear command, the logic proceeds to state 348, in which all of the duplicate directories are examined to determine if any duplicate directory memory contains an address tag corresponding to the address provided by the command.In state 350, which follows step 348, the outputs of all the comparators of the duplicate directories are examined to determine if any of the address tags are identical with the upper portion of the main memory address provided within the command. (The address tags provided to the comparators are only those addressed by the lower portion of the main memory address.) If none of the address tags match the upper portion of the main memory address, the logic proceeds from state 350 through path 352 to state 354, in which the requested data is sent to CPU 37 (Figure 2) by the main memory 50 through system controller unit 55.

If it is found that one of the address tags does match the upper portion of the main memory address, the logic proceeds from state 350 to state 356, in which the full/empty bit of that address tap is reset and the clear command is sent to the cache unit of the associated CPU. The logic then proceeds from state 356 to state 354, from which the logic re-enters state 277 and proceeds as discussed above.

If while the logic is in state 286, it is determined that the command received from the CPU 37 is a read command the logic proceeds to state 358, in which the command is examined to determine if an entry is to be made into the cache memory 110. If the information segment addressed within the main memory 50 (Figure 2) is to be written into the cache memory 110 (Figure 3), the logic proceeds from state 358 to state 360, in which the upper portion of the main memory address is written into duplicate directory memory 237 as an address tag along with the level provided by the read command within the duplicate memory 237 (Figure 4). From state 360 the logic proceeds to state 354 and proceeds as discussed above.

If during state 358 it is found that an entry is not to be made into the cache memory 110 (Figure 3) the logic proceeds through path 362 to state 364, in which duplicate directory memory 237 has the lower portion of the main memory address of the information segment to be read applied through channel 266. The comparator 264 examines the address tags received from duplicate directory memory 237 to determine if any of the address tags are identical with the upper portion of the main memory address. The logic proceeds to state 366 from state 364. If, in state 366, it is determined that none of the address tags match the upper portion of the main memory address, the logic proceeds through path 368 to state 354. The logic then proceeds as discussed above. If comparator 264 finds that an address tag is identical with the upper portion of the main memory address, the logic proceeds to state 370, in which the full/empty bit of that address tag is reset. It should be noted that the corresponding full/empty bit of cache directory 129 has previously been reset. The logic then proceeds from state 370 to state 354 and the operation of the duplicate directory and the cache memories continues as discussed above.

Claims

1. Apparatus for providing selective cache clearing within a multiprocessor data processing system to provide an information segment stored within a plurality of cache memories identical with said information segment stored within a main memory at a particular address, each cache memory connected to one processor of said multiprocessor data processing system, comprising:: a. a plurality of cache directories, each cache directory associated with one cache memory, said cache directory storing a portion of said particular address for locating said information segment within one cache memory associated therewith; b. a plurality of duplicate directories, each duplicate directory associated with one of said cache directories, one duplicate directory receiving and storing said portion of said particular address for determining if said information segment is located in said one cache memory in response to a command including said particular address; and c. at least one system controller unit operatively connected intermediate said one duplicate directory and its associated cache directory to transfer said portion of said particular address therebetween, said one system controller unit also operatively connected to transfer said command to other duplicate directories to determine if said portion of said particular address is contained therein.

2. Apparatus for data processing system having a plurality of processors connected to a main memory, said main memory capable of responding to particular address, for receiving a certain information segment for storage and providing said certain information segment for transfer, comprising: a. a cache unit for each processor, said cache unit including a cache memory containing said certain information segment, and a cache directory containing an associative address for locating said certain segment stored in said cache memory in response to said particular address, said cache directory responding to clear signals by clearing said certain information segment;; b. a plurality of duplicate directories, each duplicate directory connected to receive and store alterations in its associated cache directory and adapted to recognize if said certain information segment is located within said cache memory thereof for producing clear signals; and c. at least one system controller unit located intermediate said plurality of duplicate directories and said plurality of caches for transferring alterations in said cache directory to said duplicate directory and for transferring said clear signals from said duplicate directory to its associated cache directory.

3. A cache clearing apparatus for a multiprocessor data processing system having a main memory capable of storing and providing a certain information segment in response to a particular main memory address to a certain storage location therein, one processor producing a command to alter said certain information segment which includes said particular main memory address, comprising: a. at least one system controller unit connected intermediate said main memory and said one processor of said system, said system controller unit receiving said command; b. a plurality of duplicate directories connected to the said system controller unit to receive said command, one duplicate directory associated with said one processor, said duplicate directories except said one duplicate directory responding to said command by producing clear signals if said particular address is identified; and c. a plurality of cache units, each cache unit operatively connected to a processor, each cache unit capable of receiving and storing said certain information segment and adapted to clear said certain information segment in response to said clear signals, each cache directory in electrical communication with its associated duplicate directory through said system controller unit.

4. Cache clear apparatus as set forth in Claim 3 wherein each cache unit includes a cache memory capable of storing information segments and a cache directory adapted to determine if said certain information is stored in said cache memory from said particular address.

5. A cache clearing apparatus for a multiprocessor system, comprising: a. a plurality of cache units, each cache unit operatively connected to a processor of said multiprocessor system, each cache unit comprising a cache memory capable of storing information segments, and a cache directory adapted to determine if a certain information segment is stored within said cache memory, b. a plurality of duplicate directories, each duplicate directory associated with a cache unit of said plurality of cache units, each duplicate directory capable of determining if said certain information segment is located within said cache memory for producing clear signals; and c. at least one system controller unit located intermediate said plurality of duplicate directories and said plurality of cache units for transferring said clear signals from said duplicate directories to the cache directory of its associated cache unit, said cache unit responding to said clear signals to clear said certain information segment.

6. A cache clearing apparatus for a data processing system having a plurality of processors, said system including a main memory for storing and providing a certain information segment in response to a certain main memory address for a particular storage location therein, comprising: a. a plurality of cache units, each cache unit operatively connected to one of said processors capable of storing said certain information segments therein and providing said certain information segment to said processor in response to said certain main memory address, said cache units clearing said certain information segment in response to clear signals;; b. a plurality of duplicate directories, each duplicate directory associated with one cache unit of said cache units and determining if said certain information segment is stored within said one cache unit from said certain main memory address for producing said clear signals; c. at least one system controller unit connected intermediate said plurality of cache units and said duplicate directories and receiving a command to alter said certain information segment within said main memory for transferring said command to said plurality of duplicate directories and said clear signals from said duplicate directory to said one cache unit, said command including said certain main memory address.

7. Cache clearing apparatus as set forth in Claim 6 wherein said duplicate directory associated with said one cache unit produces said clear signals only if said command is received by said system controller unit from other than said processor connected to said one cache unit.

8. Cache clearing apparatus as set forth in Claim 6 wherein each cache unit comprises a cache directory for storing address tags and a cache memory storing certain information segments.

9. Cache clearing apparatus as set forth in Claim 8 wherein each address tag stored in to one cache directory is stored into its associated duplicate directory.

10. Cache clearing apparatus as set forth in Claim 9 wherein said certain main memory address is divided into an upper portion and a lower portion, said upper portion being stored as a particular address tag into a certain storage location within said duplicate directory and its associated cache directory as addressed by said lower portion.

11. Cache clearing apparatus as set forth in Claim 10 wherein said cache memory having a certain number of levels of storage locations addressed by said lower portion to provide a plurality of information segments with one information segment for each level at an output thereof, one level addressed by said lower portion having a storage location containing said certain information segment.

12. Cache clearing apparatus as set forth in Claim 11 wherein said one level and full/empty indicators are stored in association with said particular address tag within said duplicate directory and its associated cache directory.

13. Cache clearing apparatus as set forth in Claim 12 wherein a certain number of address tags, including said certain address tag, is provided as an output of said duplicate directory and its associated cache directory when addressed by said lower portion, said certain number of address tags equals said certain number of levels.

14. Cache clearing apparatus as set forth in Claim 13 wherein said cache unit includes a first comparator operatively connected to said cache directory and receiving said upper portion for determining if one address tag of certain said number of address tags is said certain address tag and the level thereof.

15. Cache clearing apparatus as set forth in Claim 14 wherein said duplicate directory includes a duplicate directory memory having address tags stored therein, and a second comparator operatively connected to duplicate directory memory, said second comparator receiving said upper portion for determining if any address tag of said certain number of address tags is said certain address and the level thereof.

16. A method of cache clearing for a data processing system having a plurality of processors and a main memory capable of storing information segments, comprising the steps of: a. transferring each command, which includes a main memory address for an information segment, affecting said information segment in said main memory from at least one system controller to a purality of duplicate directories, each duplicate directory associated with one processor of said processors; b. comparing an upper portion of the main memory address to a plurality of address tags, which are addressed by the lower portion of the main memory address, by said duplicate directory for producing clear signals if the upper portion is identical with a certain address tag of said plurality of address tags indicating said information segment stored in cache unit; and c. transferring the clear signals to said cache unit connected to said one processor through said system controller; and d. resetting a full/empty bit associated with said certain address tag to invalid said information segment stored within said cache unit.