JPS6267676A - Vector data processor - Google Patents

Vector data processor

Info

Publication number
JPS6267676A
JPS6267676A JP20840185A JP20840185A JPS6267676A JP S6267676 A JPS6267676 A JP S6267676A JP 20840185 A JP20840185 A JP 20840185A JP 20840185 A JP20840185 A JP 20840185A JP S6267676 A JPS6267676 A JP S6267676A
Authority
JP
Japan
Prior art keywords
vector
vector data
registers
register
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20840185A
Other languages
Japanese (ja)
Inventor
Yasuhiro Nakai
康博 中井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20840185A priority Critical patent/JPS6267676A/en
Publication of JPS6267676A publication Critical patent/JPS6267676A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To perform interelement arithmetic among vector data such as the inner product and total sum of the vector data without any deterioration in performance of a device by distributing and storing requests for the vector data in plural vector registers. CONSTITUTION:A control means 8 controls registers 1-4 and an input crossbar 7 with a normal vector instruction so that vector data inputted to the input crossbar is stored in one specified vector register. When the register is specified, on the other hand, the registers 1-4 and crossbar 7 are so controlled that elements of the vector data inputted to the crossbar 7 are inputted to and stored in a vector register (combination of registers 1 and 2 or 3 and 4) corresponding to the vector register specified with a vector instruction alternately. Consequently, processing including interelement arithmetic among the vector data such as the total sum and internal product of vectors is carried out by the combination of several instructions without any deterioration in the performance of a vector data processor.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はベクトルデータ処理装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a vector data processing device.

〔従来の技術〕[Conventional technology]

従来、ベクトルデータ処理装置は、複数個のベクトルレ
ジスタと、ベクトルデータを格納する任意のベクトルレ
ジスタを選択する入力クロスバを含み、1つのベクトル
データを1つのベクトルレジスタに格納する構成となっ
ていた。
Conventionally, vector data processing devices have been configured to include a plurality of vector registers and an input crossbar for selecting an arbitrary vector register to store vector data, and store one vector data in one vector register.

クトルデータを1つのベクトルレジスタに格納する構成
となっているので、1つのベクトルデータ内の要素間演
算を行うことはできないという欠点がある。
Since vector data is stored in one vector register, there is a drawback that inter-element operations within one vector data cannot be performed.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のベクトルデータ処理装置は、ベクトルレジスタ
に対しベクトルデータの格納を伴なうベクトル命令の発
行前に発行される命令で行なわれる指定、またはそのベ
クトル命令に付随して行なわれる指定により通常、1つ
のベクトルレジスタに格納されるベクトルデータの要素
を複数のベクトルレジスタに振り分けて格納する制御手
段を備えたことを特徴とする特 したがって、ベクトルの総和、内積などのベクトルデー
タ内の要素間演算を含む処理を、いくつかのベクトル命
令の組み合せで、ベクトルデータ処理装置としての性能
低下を招来することなく行うことが可能となる。
The vector data processing device of the present invention usually performs the following operations based on a specification made in an instruction issued before issuing a vector instruction that involves storing vector data in a vector register, or a specification made accompanying the vector instruction. The present invention is characterized by comprising a control means for distributing and storing elements of vector data stored in one vector register in a plurality of vector registers.Therefore, inter-element operations in vector data such as vector summation and inner product can be performed. By combining several vector instructions, it is possible to perform processing including the following without deteriorating the performance of the vector data processing device.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明のベクトルデータ処理装置の一実施例の
要部ブロック図、第2図F′i第1図の実施例の動作を
説明するための図である。
FIG. 1 is a block diagram of a main part of an embodiment of a vector data processing apparatus of the present invention, and FIG. 2 is a diagram for explaining the operation of the embodiment of FIG. 1.

本実施例は4つのベクトルレジスタ1.2.8゜4ヲ持
つ。ベクトルレジスタ1.2のベクトルデータ出力はベ
クトル加算器5に入力して加算され、加算結果のベクト
ルデータは入力クロスバ7によって選択され、ベクトル
レジスタ1.2,8.4のいずれかに格納されるよう構
成されている。ベクトルレジスタ3.4のベクトルデー
タ出力も同様にベクトル乗算器6に入力して乗算され、
乗算結果のベクトルデータは入力クロスバ7によって選
択され、ベクトルレジスタ1.2.3.4のいずれかに
格納される。また、入力クロスバ7には主記憶などベク
トル演算器5.6以外からのベクトルデータも入力0選
択され、ベクトルレジスタ1.2,3.4のいずれかに
格納される。制御手段8は通常のベクトル命令では指定
された1つのベクトルレジスタに対して入力クロスバ7
に入力されたベクトルデータを格納するようにベクトル
レジスタ1.2.8.4.入力クロスバ7を制御し、ベ
クトルデータをベクトルレジスタに振り分けて格納する
が、指定が行なわれた場合、ベクトル命令で指定された
ベクトルレジスタと対志するベクトルレジスタ(ベクト
ルレジスタ1とベクトルレジスタ2またはベクトルレジ
スタ3とベクトルレジスタ4の組み合せ)に入力クロス
バ7に入力されたベクトルデータの要素を交互に入力格
納するようにベクトルレジスタ1.2.8.4、入力ク
ロスバ7を制御する。
This embodiment has four vector registers 1.2.8°4. The vector data output of vector register 1.2 is input to vector adder 5 and added, and the vector data resulting from the addition is selected by input crossbar 7 and stored in either vector register 1.2 or 8.4. It is configured like this. The vector data output of the vector register 3.4 is similarly input to the vector multiplier 6 and multiplied.
Vector data resulting from the multiplication is selected by the input crossbar 7 and stored in one of the vector registers 1.2.3.4. Furthermore, vector data from sources other than the vector calculator 5.6, such as the main memory, is also input to the input crossbar 7 and is selected as input 0, and stored in either of the vector registers 1.2 and 3.4. In a normal vector instruction, the control means 8 controls the input crossbar 7 for one specified vector register.
Vector registers 1.2.8.4. The input crossbar 7 is controlled and vector data is distributed and stored in vector registers, but if a designation is made, the vector register (vector register 1 and vector register 2 or vector register The vector registers 1.2.8.4 and the input crossbar 7 are controlled so that elements of the vector data input to the input crossbar 7 are alternately input and stored in the combination of the register 3 and the vector register 4.

次に、本実施例の動作をベクトルの内積を求める場合を
例にとって第1図、第2図を参照して説明する。
Next, the operation of this embodiment will be described with reference to FIGS. 1 and 2, taking as an example the case of calculating the inner product of vectors.

今、内積を求める2つのベクトルを8要素のペクト””
 =(aOr ’Im ”’ * a5. a7 )と
B=(bOn ble・・・、b6.b7)とする。ま
ず、ベクトルデータA。
Now, calculate the inner product of the two vectors with 8 elements.
= (aOr 'Im ''' * a5. a7 ) and B = (bOn ble..., b6. b7). First, vector data A.

Bはベクトルレジスタ8.4に第2図(1)に示すよう
に格納される。次にベクトルレジスタ1.2に演算結果
を振り分けて格納するベクトル乗算命令を発行すると、
ベクトルレジスタ1.2には、第2図(2)に示すよう
に演算結果のベクトルデータが格納される。次にベクト
ルレジスタ1.2に演算結果を振り分けて格納するベク
トル加算命令を2回発行するとベクトルレジスタ1.2
は第2図■、(4J参F詩に示すようになる。最後にベ
クトルレジスタ1に演算結果を格納するベクトル加算命
令を発行すると、第2図(5)に示すようにベクトルA
、Bの内積カニ求まる。
B is stored in the vector register 8.4 as shown in FIG. 2(1). Next, if you issue a vector multiplication instruction that distributes and stores the operation results in vector registers 1.2,
The vector register 1.2 stores vector data as a result of the calculation, as shown in FIG. 2 (2). Next, when a vector addition instruction is issued twice to distribute and store the operation results in vector registers 1.2, vector registers 1.2
will be as shown in Figure 2 ■, (4J reference F).Finally, when a vector addition instruction is issued to store the operation result in vector register 1, the vector A will be added as shown in Figure 2 (5).
, find the dot product of B.

ココテ、明らカナヨうに第2図(21,(31,(41
,(51はベクトルデータの要素の総和を求める動作で
あり、最初ベクトルレジスタ1.2に総和を求めるベク
トルを撮す分けて格納しておき、ベクトルレジスタ1.
2に演算結果を振り分けて格納するベクトル加算命令を
ベクトルレジスタ1.2に格納される演算結果の要素数
が1に々るまで発行し、最後に要素数1で通常のベクト
ル加算命令を発行すれば総和が求まる。また、この動作
をベクトルレジスタ8.4とベクトル乗算命令におきか
えればベクトルデータの線種を求めることができる。
Kokote, obviously Kanayo Uni Figure 2 (21, (31, (41)
, (51 is an operation for calculating the sum of the elements of vector data. First, the vector for which the sum is to be calculated is separately stored in vector registers 1.2, and then the vectors are stored separately in vector registers 1.
Issue vector addition instructions that distribute and store the operation results in vector registers 1 and 2 until the number of elements of the operation results stored in vector registers 1 and 2 reaches 1, and finally issue a normal vector addition instruction with 1 element. The sum can be found. Furthermore, by replacing this operation with vector register 8.4 and a vector multiplication instruction, the line type of vector data can be determined.

なお、これらベクトルデータの総和、線種を求める動作
では、ベクトルデータの要素数が9m(乳は正の整数)
でなければ演算結果に影響を与えない値をベクトルデー
タの要素として、追加要素数が2mになるようにする処
理が必要であるが、その詳細については省略する。また
、詳細な説明は省略するが、その他の実施例として複数
の入力データの比較を行ない、指定によって大きい要素
または小さい要素を出力するベクトル演算器を持つ場合
、上で述べた総和を求める場合と同様のベクトル命令の
組み合せでベクトルデータの最大値要素または最小値要
素を求めることができる。
In addition, in the operation of calculating the sum of these vector data and the line type, the number of elements of the vector data is 9m (the milk is a positive integer).
Otherwise, it is necessary to use values that do not affect the calculation results as elements of the vector data so that the number of additional elements becomes 2m, but the details thereof will be omitted. Although detailed explanations are omitted, as another example, a vector calculator that compares multiple input data and outputs a larger element or smaller element depending on the specification is used, and when calculating the sum as described above, The maximum value element or minimum value element of vector data can be determined by combining similar vector instructions.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ベクトルレジスタへのベ
クトルデータの格納において複数のベクトルレジスタに
ベクトルデータの要素を振り分けて格納することにより
、ベクトルデータの内積総和などのベクトルデータ内の
要素間演算を行なうことができる効果がある。
As explained above, the present invention distributes and stores elements of vector data in a plurality of vector registers when storing vector data in a vector register, thereby performing inter-element operations in vector data such as the sum of inner products of vector data. There are some effects that can be done.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のベクトルデータ処理装置の一実施例の
ブロック図、第2図は第1図の実施例の動作を説明する
ための図である。 1.2.f3.4・・・ベクトルレジスタ、5・・・ベ
クトル加算器、 6・・・ベクトル乗算器、 7・・・入力クロスバ、 8・・・制御手段。 特許出願人  日本電気株式会社 第2 図
FIG. 1 is a block diagram of an embodiment of a vector data processing apparatus of the present invention, and FIG. 2 is a diagram for explaining the operation of the embodiment of FIG. 1. 1.2. f3.4... Vector register, 5... Vector adder, 6... Vector multiplier, 7... Input crossbar, 8... Control means. Patent applicant: NEC Corporation Figure 2

Claims (1)

【特許請求の範囲】 複数個のベクトルレジスタと、ベクトルデータを任意の
該ベクトルレジスタに選択して、格納する入力クロスバ
とを含むベクトルデータ処理装置において、 前記ベクトルレジスタへのベクトルデータの格納を伴な
うベクトル命令の発行前に発行される命令で行なわれる
指定、または該ベクトル命令に付随して行なわれる指定
により、通常1つの前記ベクトルレジスタに格納される
ベクトルデータの要素を複数の前記ベクトルレジスタに
振り分けて格納する制御手段を備えたことを特徴とする
ベクトルデータ処理装置。
[Scope of Claim] A vector data processing device including a plurality of vector registers and an input crossbar for selecting and storing vector data in any of the vector registers, An element of vector data normally stored in one vector register can be transferred to a plurality of vector registers by a specification made in an instruction issued before a vector instruction is issued, or a specification made accompanying the vector instruction. 1. A vector data processing device characterized by comprising a control means for distributing and storing data into vector data.
JP20840185A 1985-09-19 1985-09-19 Vector data processor Pending JPS6267676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20840185A JPS6267676A (en) 1985-09-19 1985-09-19 Vector data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20840185A JPS6267676A (en) 1985-09-19 1985-09-19 Vector data processor

Publications (1)

Publication Number Publication Date
JPS6267676A true JPS6267676A (en) 1987-03-27

Family

ID=16555640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20840185A Pending JPS6267676A (en) 1985-09-19 1985-09-19 Vector data processor

Country Status (1)

Country Link
JP (1) JPS6267676A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5532161A (en) * 1978-08-29 1980-03-06 Fujitsu Ltd Integration processing unit
JPS5727360A (en) * 1980-07-25 1982-02-13 Fujitsu Ltd Accumulation instruction processing system
JPS6072069A (en) * 1983-09-28 1985-04-24 Nec Corp Vector operation processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5532161A (en) * 1978-08-29 1980-03-06 Fujitsu Ltd Integration processing unit
JPS5727360A (en) * 1980-07-25 1982-02-13 Fujitsu Ltd Accumulation instruction processing system
JPS6072069A (en) * 1983-09-28 1985-04-24 Nec Corp Vector operation processor

Similar Documents

Publication Publication Date Title
US6539368B1 (en) Neural processor, saturation unit, calculation unit and adder circuit
US4385363A (en) Discrete cosine transformer
US8891757B2 (en) Programmable cryptographic integrated circuit
EP0314809B1 (en) Vector processor for processing recurrent equations at a high speed
JPH0793294A (en) Two-dimensional discrete cosine transformation device two-dimensional inverse discrete cosine transformation device and digital signal processor
KR20190107766A (en) Computing device and method
Chionh et al. Fast computation of the Bezout and Dixon resultant matrices
JPH04242861A (en) Inner product arithmetic circuit
JPH0477932B2 (en)
JPS6267676A (en) Vector data processor
Goertzel Lagrange interpolation on a processor tree with ring connections
JPS6310263A (en) Vector processor
JP2696903B2 (en) Numerical calculator
JP3691538B2 (en) Vector data addition method and vector data multiplication method
JPH01145771A (en) Pipe line calculator
Murray Microprocessor system for TV imagery compression
SU741274A1 (en) Device for computing sine-cosine products
EP4374262A2 (en) Multi-lane cryptographic engines with systolic architecture and operations thereof
JPH03142671A (en) Automatic selection system for fft arithmetic method
JPH02235174A (en) Bus matrix
JP2001202019A (en) Parallel ellipse arithmetic unit and its program recording medium
JPS60144876A (en) Inter-vector element arithmetic device
KR20230164944A (en) Processing apparatus and operating method thereof and electronic apparatus including the processing apparatus
KR960016574A (en) Signal processing equipment
JPH06110852A (en) Block-shaped parallel decentralized operational array processor