JPH02235174A - Bus matrix - Google Patents

Abstract

PURPOSE: To execute a dual operation and to improve the performance of a processor by providing a multiplier device multiplying operand inputs, an adder device adding them and a data route controller connected to operand input. CONSTITUTION: A controller 12 constituted of a multiplexer selects that the operand (OP) 1 of the multiplier device 24 becomes either KR from a register 22, KI from a register 21 or SRC1 from a line 20. A controller 25 selects that OP2 becomes SRC2 from a line 26 or the final result of the adder device 32 from a line 34. Controllers 31 and 33 select necessary inputs for OP1 and OP2 in the device 32. The result of the device 32 is connected to one of 32 floating point registers by the line 34. Thus, a bus matrix with which the dual operation is executed in the floating point device of the processor is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor microprocessors, and more particularly to path matrices that perform dual arithmetic operations.

BACKGROUND OF THE INVENTION The present invention relates to path matrix circuits forming part of floating point units in microprocessors. The microprocessor used in connection with the present invention is an Intel 860" microprocessor designated as the NIO TM7'a processor (Intel is a registered trademark of Intel Corporation). 2/6 4 bit I EEE
Compatible floating point processor, 32-bit RIS
O integer processor, and a 64-bit 3D graphics processor. Using a K-optimized order value processor for both vector and scalar operations, it is possible to use an industrial processor with more than a million transistors and about half the performance of Cray 1 on a single chip. Becomes a primary integrated high-performance vector ●processor. NIO processors use pipelined floating point units to obtain very fast execution speeds.

As discussed below, the present invention provides a path matrix that is fully optimized for floating point hardware in the N10 processor. This bus matrix supports simultaneous (dual) operation of multiplier units and adder units. These dual operations are the most common K
Software used ● Supports summation algorithms such as product, DAXPY, FFT, etc.

Generally, for microprocessor instructions, the source operand and destination are specified to come from a set of floating point registers. In most devices, this set of floating point registers typically provides two source operands and one destination operand. Perform simple addition or multiplication operations
A three operand configuration is sufficient for . However, to perform dual operations such as simultaneous operations or multiplications, three more operands (six operands in total) are required. There is no need for a floating point register file to handle six operands.
Because of the lack of efficiency, conventional microprocessors typically perform dual operations sequentially. In other words, first we perform addition, then multiplication, and vice versa.

Another method of sequential operations is to perform both multiplication and addition operations in parallel. This method is a widely used method known as the multiply-accumulate operation. In the multiply-accumulate operation κ, the multiplier is a floating point register.
Obtain the source-operand of 2') from the file. One of the adder's operand inputs receives the result output of the multiplier.

The adder's other sources ● Oberand inputs are connected to the adder's own result outputs to form a kind of feedback configuration. A simulated arithmetic operation is essentially an accumulation of sums of products. However, the multiplication and accumulation operation has a problem in that it can only perform simple operations such as the sum of products. This is because the interconnects are typically fixed-structure, do-wired.In response to the demands of providing a variety of algorithms, they are virtually universal and can handle a wide range of operations. What is needed is an apparatus that advantageously has a bus matrix capable of feeding complex algorithms in a highly efficient manner. This ability increases the performance of the microprocessor described here compared to traditional processors.

[Overview of the invention]

A bus matrix for dual arithmetic operations in a microprocessor capable of performing floating point operations is explained. The microprocessor provides first and second floating point source instruction operands and floating point destination g/φ registers. A multiplier is used to multiply the first and second operands to produce a first result. The adder device has the third and fourth
Used to add operands to produce a second result. The invention also includes a register device for storing the conjunctive and imaginary parts of constants used to perform inner loop calculations for a given algorithm and for temporarily storing the first result generated by the multiplier. I'm here. The data path controller implements a predetermined algorithm in parallel.
It is used to select one of a plurality of operands to connect to each operand input of the multiplier and adder. This feature of the invention allows both multiplication and addition operations to be performed in parallel to provide a wide variety of algorithms in a microprocessor.

Finally, multiple operands (first result, second result, first
and a second source operand, a constant, containing the temporarily stored first result) are interconnected in a bus mask for connection to inputs of all data routing devices. For a given algorithm, the data path controller determines which particular output input should be connected to the appropriate input of either the multiplier or the adder. For example, in an embodiment of the present invention, 16
Sixteen different data paths are shown serving different software instructions or algorithms.

Embodiments of the present invention will be described below with reference to the accompanying drawing K.

〔Example〕

A floating point path used to perform parallel arithmetic operations.
Explain the matrix. In the following explanation,
It will be apparent to those skilled in the art that the detailed descriptions, such as specific data paths, are provided to aid in understanding the invention, and the invention is not limited to these details. Also,
Detailed descriptions of well-known structures and circuits, such as adders and multipliers, are omitted so as not to obscure the present invention.

In many modern microprocessor architectures, floating point units use parallelism to increase the speed at which operations are delivered to the unit. One type of parallelism is called bilining. The pie-grain architecture processes each operation as a series of more basic operations (called "stages") that can be executed in parallel. For example, consider the floating-point adder unit of a processor. The operation of is expressed as ▲, and the stages are expressed as ▲1, ^2, and A3. The stages are specified such that A1+1 regarding one Agu instruction can be executed in parallel with A1 regarding the next Agu instruction. , each Ai can be executed in exactly one clock. Note that the pipe two innings of the processor's multiplier and vector integer unit can be described similarly, except that the number of stages is different.

FIG. 1 illustrates three-stage bilining as found in the floating point adder (or floating point multiplier if a single precision input overland is used) of a processor incorporating the present invention. Each row L in the figure shows one of the three stages of the vibe line.

Each stage holds immediate results and (if provided by software to the first stage) state information regarding these results. Also, in the drawing, the instruction stream consists of a series of nine consecutive floating point instructions, all of the LAL class (ie, all adda instructions or all single precision multiplier instructions).

The temporal relationship of the instructions is f, + 1 + 1 + 1 ”
It is expressed as 2 + etc. The rows of the diagram represent the state of the device during successive clock cycles K. Each time a pipeline operation is performed, the state of the last stage is made available in a status register (eg, in a NIO processor, the result is available in a floating point status register "fsr"). The result of the final stage of the pipeline is stored in %rde+st, the pipeline is advanced one stage, and the input operands arcl,
sr-c2 is transferred to the first stage of the pipeline.

The two-monics srcl, src2, rdest refer to one of the 32 floating point registers located in NIO processor K.

In the NIO processor, the number of pipeline stages is 1.
~3 pieces. Pipeline operations related to the three-stage pipeline K store the results of the three previous operations. A pipeline operation related to a two-stage pipeline stores the result of the two previous operations. Pipeline operations related to the one-stage pipeline K store the results of previous operations. The NIO processor has multiplier, adder, vector-to-integer unit, and floating point pipelines. The adder pipeline has three stages. The number of multiplier stages in the pipeline depends on the precision of the pipeline's source operands, with two stages being three stages. The vector-integer unit has one stage for full precision.

Load ● The pipeline has three stages for total precision.

FIG. 2 shows an embodiment of the invention. The floating point path matrix of FIG. 2 includes a multiplier unit 24 and an adder unit 32. The internal configuration of the devices 24 and 32 is as follows:
In simple terms, these consist of conventional digital multipliers or adders, although they are well known in the art and will not be discussed here. This embodiment is based on the title of the invention "4-4 for parallel multiplication" passed to the applicant Kgl
Two US patent applications, ``27 Dar Cell'' and ``Statsky Bit Predictor for Floating Point Multiplication'', are disclosed in two US patent applications using a nine multiplier device. The adder device of this embodiment is assigned to the applicant of the present invention, and has two United States Patent No. Disclosed to patent advisor.

As shown, the bus matrix further includes three special registers: KR register 22, KI register 21, and T register 30 (KI is the imaginary part of the constant, KR is the real part of the constant, and T indicates temporary)
. These registers can store values from one dual arithmetic instruction and provide them as inputs to subsequent dual arithmetic instructions. Constant register 22.2
1 can be used to store the real and imaginary parts of the operand srcl, respectively. After that, sr.
These values can then be fed into the multiplication pipeline instead. The T (temporary) register 30 is useful for storing the result of the last stage of the multiplier pipeline and then providing its value to the adder pipeline on behalf of srcl.

FIG. 2 also shows data path control devices 23, 25, 31.
．． 33 is shown. Data path controller 23.25
, 31.33 are used to select the operand inputs of the multiplier unit and the adder unit. Each of these controllers (represented by a single horizontal line in FIG. 2) typically includes a switching device such as a controllable bus. This embodiment uses conventional multiplexers well known in the art.

In operation, multiple operands (indicated by arrow K pointing towards the horizontal line indicating the data path controller)
One operand is selected from , and multiplier t9 is connected to one of the adders. 9. For example, the data path controller 23 may
Either the imaginary value of the constant stored in KIK, the real value of the constant stored in KR, or the source operand srcl is applied to the first operand input of multiplier unit 24.

In this embodiment, each multiplexer 23, 25, 31
, 33 is controlled by a 4-bit output path control field (DPC) using an Op code. DPC specifies special register loading and operands.

FIG. 2 shows the total bus connection matrix used to demonstrate all of the possible algorithms supported by embodiments of the present invention. Operand 1 of multiplier unit 24 is selected to be either KR supplied from register 22, Kl from register 21, or grcl supplied along line 20. By determining one of these values, the operand 1 (apl) of the multiplier is determined by the specific engineering coding κ of the DPC. Similarly, the multiplier obed2
(op2) is arc2 supplied from line 26
, or the result of the final stage of the adder pipeline occurring on line 34. Controller 25 determines which of these two values will be operand 2. Operand 1 of the adder is the ac connected to 2iy2G.
rl,? This will either be the temporary result value stored in register 30K, or the result of the last stage of the nine adder pipeline inputs along line 34. The controller 31 is used to select the appropriate data path for one of the operands of the adder device 32. Finally, operand 2 of adder 32 is either src 2 from line 26, the result of the last stage of the multiplier pipeline on line 2T, or the result of the last stage of the adder pipeline supplied on line 34. The 5K will be chosen. The controller or multiplexer device 33 is instructed by the DPC to select which input operand becomes operand 2 of the adder device 32. The results provided by adder device 32 along line 34 are sent to processor 32.
rdest connected to one of the floating point registers
It has value.

Table 1 shows how various technical coding of the DPC selects different data paths and therefore provides different algorithms. Each member of the DPC has a unique set of 21 Monics associated with it. 21 Monics PFAM, PFSM C. Dual arithmetic instructions "Pipeline floating point addition and multiplication" and "Pipeline floating point subtraction and multiplication." The actual data paths taken are shown in FIGS. 3-8.

Table I DPC Encoding - When K load is set, multiplier operand 1 is
If R then KR is loaded and operand 1 of the multiplier is K
If L, KL is loaded.

For example, consider the case where a programmer wants to perform a matrix inversion. In the present invention, this is the third
This is done using the software instruction r2pl shown in the actual data path of the figure.

When performing matrix inversion, the inner loop of the algorithm is represented by the following mathematical relationship:

kV 凰 + V! →V. ζ, k is a real constant, V,,V. is a vector element. Performing a matrix inversion involves multiplying each vector element by a constant and then adding a second vector to the result, whereby the result is stored back in a second vector storage location. . To provide this instruction, in FIG. 3, the KR register is connected directly to the apl input of the multiplier unit. The other input (op2) of the multiplier unit is the floating point instruction operand s
rc2K is connected. The output result of the multiplier device is connected to the op2 power of the adder device and the adder device toopl
The input is connected to the srcl instruction operand of the floating point unit. The srcl and src2 operands correspond to v11 v in the above equation. The result from the adder device is placed in the rdeit register and vector V! becomes the new value for

Matrix inversion is a suitable example of a dual operation involving an inner loop constant, which can be performed with the bus matrix of the present invention, but cannot easily be performed using conventional multiply-accumulate operations. Multiply-accumulate methods are generally less accurate, more difficult to program, and slower to obtain results, making them less desirable. (It should be noted that conventional multiply-accumulate operations are provided by ml2apn software instructions such as those provided in the path matrix of the present invention.) The present invention is not limited to the embodiment shown herein; It will be obvious to those skilled in the art that various modifications can be made without departing from the idea of the invention.

For example, although various algorithms are shown here that may be provided, other matrix connections may be used to provide different algorithms.

As described above, the present invention provides an excellent path matrix for performing dual arithmetic instructions in a floating point unit of a microprocessor.

[Brief explanation of the drawing]

FIG. 1 shows the following processor pipeline architecture related to the floating-point bus matrix of the present invention.
FIG. 2 shows an embodiment of the bus matrix of the invention, and FIG. 3 shows l! j! 1 shows the actual data paths selected for two monitors r2pl, r2sl, each representing a specific software instruction, and FIG. -Monique r2pt
, r2stK, and FIG.
FIG. 6 shows the actual data paths selected for the 21 monitors r2apt and r2amt, each representing a particular software instruction, as shown in Table 1; The figures show the actual data paths selected for the two-monics i2pl, 12ml, each representing a specific software instruction, as shown in Table 1, and FIG. 21 Monique i2pt, which represents
12st, FIG. 9 shows two monitors 12apl, 12asl, each representing a specific software instruction, as shown in Table 1.
FIG. 10 shows the actual data paths selected for two monitors 12apLi2ast, each representing a particular software instruction, as shown in Table 1, and FIG. Table 1 shows the actual data paths selected for the two monitors ratlp2, ratlg2, each representing a specific software instruction, and FIG. Figure 13 shows the actual data path selected for the 21 Monique m12 tatami pm, ml2 asm, as shown in Table 1.
21 Monik r, each representing a specific software instruction.
14 shows the actual data paths selected for ilp2, rals2, and the binary ml2tt, each representing a specific software instruction, as shown in Table
15 shows the actual data paths selected for pa, ml2ttsa, and FIG.
p2. The actual data paths selected for iatls2 are shown in Figure 16, each representing a specific software instruction, as shown in Table 1.
Figure 17 shows the actual data path selected for mlml2tam, and FIG.
18 shows the actual data path selected for imls2, and FIG.
3 shows the actual data path selected for l2tsa. 24・●φ・multiplier device, 32・●●−adder device, 23.25 ,33 φ data path control device, ●KL register, 22 ● 7I[逼−1 ●KR register, 30 ● . T register.

Claims (3)

[Claims] (1) a multiplier having first and second operand inputs and an output providing a first result; and an adder having third and fourth operand inputs and an output providing a second result; selecting one of a plurality of operands including the first result, the second result, and first and second source operands to each operand input of the multiplier and the adder to provide an algorithm of A dual arithmetic bus matrix comprising: a data routing device connected to the bus matrix; (2) in a processor having a floating point unit and providing first and second floating point instruction operands, a multiplier unit that multiplies the first and second operands to produce a first result; an adder device that adds four operands to produce a second result; a register device that stores a constant and temporarily stores said first result; and an adder device that adds four operands to produce a second result; connected to the multiplier so that another one of the plurality of operands becomes the second operand,
a multiplexer device connected to the adder device such that one of the plurality of operands becomes the third operand and one of the plurality of operands becomes the fourth operand to supply a predetermined dual operation algorithm; , A processor that executes dual arithmetic instructions. (3) In a floating point section of a processor having a floating point multiplier and a floating point adder and supplying first and second floating point instruction operands, a register device for storing constants and the result of the final stage of the multiplier. and, related to each operand input of the multiplier and the adder,
and the first and second instruction operands, the constant, the result of the last stage of the multiplier, the result of the current stage of the multiplier, so as to provide a software algorithm by performing multiplication and addition operations simultaneously. , the result of the current stage of the above adder and one of the multiple operands it contains.
a data routing device connecting one of said operands to said associated operand input; and a bus matrix for executing dual instructions.