JPS5452945A - Floating decimal point arithmetic control unit - Google Patents
Floating decimal point arithmetic control unitInfo
- Publication number
- JPS5452945A JPS5452945A JP11904077A JP11904077A JPS5452945A JP S5452945 A JPS5452945 A JP S5452945A JP 11904077 A JP11904077 A JP 11904077A JP 11904077 A JP11904077 A JP 11904077A JP S5452945 A JPS5452945 A JP S5452945A
- Authority
- JP
- Japan
- Prior art keywords
- register
- prenormalization
- decimal point
- circuit
- operand
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To eliminate the overhead of prenormalization st the arithmetic unit by performing the prenormalization to be the overhead of the floating decimal point arithmetic prior to storage into the operand anticipating buffer.
CONSTITUTION: The floatng point data which is obtained from the main memory through the operand anticipation enters prenormalizing circuit 9 and is set to register 1. The prenormalizing action is given to the data when prenormalization control bit 8 is on. The mantissa part of register 1 receives a check for necessity of prenormalization via zero digit detecting/counting circuit 2 and is then shifted (4) to be set to register 5. The exponent part is corrected (3) based on the shift count given from circuit 2 and is then set to register 5. The prenormalized data of register 5 is stored in operand anticipating buffer 6 to be then sent to floating decimal point arithmetic circuit 7
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11904077A JPS5452945A (en) | 1977-10-05 | 1977-10-05 | Floating decimal point arithmetic control unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11904077A JPS5452945A (en) | 1977-10-05 | 1977-10-05 | Floating decimal point arithmetic control unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5452945A true JPS5452945A (en) | 1979-04-25 |
Family
ID=14751450
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11904077A Pending JPS5452945A (en) | 1977-10-05 | 1977-10-05 | Floating decimal point arithmetic control unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5452945A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS592140A (en) * | 1982-06-29 | 1984-01-07 | Fujitsu Ltd | Pre-normalizing system |
JPS6083139A (en) * | 1983-10-13 | 1985-05-11 | Nec Corp | Normalizing circuit of binary-coded decimal number |
-
1977
- 1977-10-05 JP JP11904077A patent/JPS5452945A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS592140A (en) * | 1982-06-29 | 1984-01-07 | Fujitsu Ltd | Pre-normalizing system |
JPS6083139A (en) * | 1983-10-13 | 1985-05-11 | Nec Corp | Normalizing circuit of binary-coded decimal number |
JPH0366692B2 (en) * | 1983-10-13 | 1991-10-18 | Nippon Electric Co |
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