JPS6083139A - Normalizing circuit of binary-coded decimal number - Google Patents

Abstract

PURPOSE:To attain a high-speed operation of a normalizing circuit of binary- coded decimal number by shifting the input data after detecting ''1'' that is most approximate to the most significant bit of the input data. CONSTITUTION:A preceding ''1'' detecting circuit 1 uses the data X of mantissa part as an input and detects ''1'' most approximate to the most significant bit MSB including this MSB and informs this detection information to an encoder 2. The encoder 2 converts the number of shifts into a code of binary display to perform normalization according to the received information. A shifter 3 obtains the input of the data X and shifts the data X according to the shift information which is coded by the encoder 2 to produce the nomalization data Y. This circuit ensures a normalizing action at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a normalization circuit that is necessary in the processing process of an arithmetic device that handles binary coded 10-decimal (BCD) data. I will explain about it. The format of a decimal floating point number is usually divided into an exponent part and a mantissa part, as shown in FIG.

N=m@lOm: Provisional ee a Exponent part The normalization referred to here is to maximize the number of significant digits within a given format. , l digit to 1
This is to shift the entire mantissa so that the digit) becomes a ``missing 0'' (not a ``0''). The format normalized under μ will be called a normal number. Next, let's explain the normal number ft using an example. ◎Now, suppose 0.053X10'
If we have the data, this value is (1) 0.053X10' (2) 0.530X]0
' (3) Although it is expressed many times as in 5.300 It has been shifted. Here, a series of processing will be described using subtraction as an example of decimal floating point operations. To simplify the explanation, data
, the processing process will be outlined for an example of subtracting data Y1 of 9.525X10'' from .

Examples

In this example, FIX1=1.832X]0” yt==0.
952×10”.

(2) Subtraction Subtract the mantissas of Xl and Yl.

1.832 - 0.952 = 0.880 (j Normalization of operation result The above subtraction gives an operation result of 0.880 Among them, the "NO# digit" that is one scan closer to the MSD, including MSDffi, is detected and shifted to the left by the number of digits of @θ" in front of it (digits in the above example). At this time, the exponent value f'122-];21, the normalized value is 8.800 The specific gravity is also heavy.As for the left shift method for normalization, use hardware with a 1-digit left shift function, and repeatedly shift the left shift while checking whether the MSD of the mantissa becomes 'NO#'. I can think of things to shift◎
However, with this method, as the number of L'0's that actually requires checking and shifting of the MSD for the number of consecutive '0' digits of the mantissa increases, the time required for normalization increases. becomes long.

Therefore, even if other preprocessing and calculation processing can be executed at high speed, if the time required for normalization is large, the overall floating point calculation speed will be significantly reduced.

Therefore, as a method to achieve normalization at high speed, a method is considered that includes the MSD of the data, detects the NO" digit closest to the MSD, and shifts the data to the left at once by thick so that the MSD becomes 5". The present invention is based on binary evolution 1
Most significant bit of decimal data (hereinafter referred to as rMsBJ)
? - A leading detection circuit for detecting "1#" closest to the MSB, an encoder for determining the number of shift bits in units of 4 bits according to its output information, and an encoder for actually determining the number of shift bits according to the determined number of shift bits. The present invention provides a binary coded decimal number normalization circuit that is configured with a thick circuit that performs a shift of 2
Data expressed in evolved lO base number (BCD) is input, and the most significant bit of the data is
a preceding one detection circuit that detects "1#" closest to B; an encoder that converts the output information from the preceding one detection circuit into shift information in units of 4 bits; According to the present invention, it is possible to obtain a binary coded decimal normalization circuit that operates at high speed with a simple circuit configuration. 2 is a block diagram of a binary IO base normalization circuit which is an embodiment of the present invention. l is mantissa data X
2 is an encoder that converts the output of the preceding first detection circuit into a code vcW corresponding to the bit position;
3 is the data X? based on the code obtained by the encoder. 7 lids for normalized data YIC conversion.

The preceding one detection circuit l receives mantissa data X as input, and M
SBk dizziness detects '1# closest to MSB and informs the encoder 2 of the information ◎The encoder 2 converts the shift number for normalization into a code in binary representation according to the received information. Next, in jitter 3, the data X is input, and according to the shift information encoded by the encoder 2, the @cipi data X is shifted to create normalized data Y'&. Figure 6 is a truth value diagram of the preceding detection circuit 1 and the encoder 2. Now, the data length of the data to be normalized to the temporary one is K1 - 16 bits (4 digits)
Then, depending on the number of consecutive 10" bits from the MSB, excluding all 0 pits, it is divided into 16 pieces of data. ◎For the 16 pieces of data, the output 815 is selected by the preceding one detection circuit. ~SO, and also the output of the encoder 2 and the number of bits corresponding to the output code. Fig. 3 shows a first embodiment of the preceding one detection circuit 1 and the encoder 2.1- 15, 1-14.1-13...
...1-1.1-0 is a block with the same logical structure, 1
logical blocks 1-n (hereinafter n=on1+2...
...15) is composed of a precharge transistor Pn%NOR gate Mn, an inverter N, and a switch transistor Rn, and includes the MSB of input data, M
Selection aS corresponding to the pit position of 'l'' closest to SB
In this circuit, n (any one of 5lll-So) becomes active. The encoder 2 includes a transistor Tr2 that precharges the output lines Et and Es, and a transistor Q controlled by the output Sn from the preceding detection circuit 1.
Outputs a code (including information regarding the number of shift bits) corresponding to the first pit position by a valid selection line of Sn. Output to m' E o to E s. Output lines E, , g.

is always output as 10''. Fig. 7 is a table showing the positions of transistors Q and ~Qln of encoder 2. This encoder 2 (C outputs shift bits a?E, ~E0 in binary notation.・Next, the operation of the first embodiment shown in FIG. 3 will be explained in detail. First, when φ1 is "L"
OE is “0” +7) (!: Ki, NOR game day 4
(7) Output A;) f ``O'' with te, discharge transistor Trlid off, precharge transistor pHl~Pal''j on, zero transmission signal line B□~
BG is precharged. When the biJ record transmission signals BIII to Bo become '1', the NOR gate f
%its-MO output S15""S.

are all 1″0″. On the other hand, in the encoder 2, the gate circuits Q1 to Qm are all turned off, the precharge transistor Tr2 is turned on, and the output lines E3 and E are all precharged to 'l'.Next, 01 transitions to '0'. , at this time, if the control signal LOg is active (0''), the output A of the NOR gate 4 is not ``1'', and the discharge transistor Tri is turned on and the 4 transmission signal line B is turned on.
l becomes '0'' ◎At this time, logical block 1-15
When data D15 input manually is @0#, inverter N
The output of i5 is '1'', and the switch transistor R1
g is turned on, and the zero transmission signal line B14 of block 1-14 also becomes Qo$1. That is, the switch transistor R
n provides means for transmitting a zero transmission signal from the upper level to the lower level if the input data is '0', and not transmitting it if it is '1'. Also, at this time, the input data ID1s is '0' and the output of the inverter N15 is 61#, so the NO
The output of R gate M1B is set to 0''.

On the other hand, when the input data D1B is "1", the output of the inverter N15 is "@0", the switch transistor 1 (15 is turned off, and the zero transmission signal line B14 of the logic block 1-14 is "1"). The outputs 814 to 814 from the logic blocks 1-14 to 1-0 remain charged, and the subsequent zero transmission signal lines B13 to B0 also remain charged to 1#.
S0 remains @0”. However, logical block 1-
The zero transmission signal line B1 of 15 becomes ``O'', and as mentioned above, since the output of inverter N15 is ``O'', the output st's from NOR gate IB transitions to ``P1''. . Therefore, the logic block 2-1 of encoder 2
5 transistors Ql and Qz are turned on, and the output line E2
r E3 is discharged and E3 to E0 are all '
0". In other words, the input data I)ts is 11
When h, output E of encoder 2. ~E3 is everything'
According to Mari in Table 1, the shift bit number serves as a control signal indicating that the number of bits to be shifted is 0. Generally, when φ1 is '1'' and control signal LOE is 60'', the output A of the NOR gate 4 is 0'', the discharge gate 2 transistor Tri is off, and the precharge transistor Pn (n = 0 to 15) is on. Therefore, the zero transmission signal lines BIS-B0 are precharged to 11'. When the zero transmission signal lines BIB-B0 become '1', the outputs 816-S0 of the NOR gate Mn all become 'θ'. ,
In encoder 2, all gate circuits Q1 to Qm are turned off, precharge transistor Tr2 is turned on, and output line E is turned off.
,, E, are precharged to 1″.

Next, 01 transitions to 60", and the control signal LOE power;"'o
When the output is "0", the output A of the NOR gate 4 becomes "1", the discharge transistor Tri is turned on, and the zero transmission signal line 13ts becomes "0".At this time, if the input data DIS is "0", the inverter I 'The output of Jts is @
1", the p1 switch transistor gts is turned on,
Zero transmission signal line B144″ of next stage logic block 1-14
'O' and input data Dn (n=0 to 15) is al
The zero transmission signal Bn (n=0 to 1
5) is transmitted as "'0". In the logic block l-m where the input data Dn is 61", the switch transistor Rm is turned off, and the logic block 1-n (n: 0 to m-
1) zero transmission signal, ljB n (n = O ~ m-1)
remains "1". At this time, output lines 80 to 815
is a logic block l − whose input data Dn is “1”
Only the output line am of m is 61", other logic blocks 1-n (n, = 0 to m -1, m+1 to 15)
Output line 8 n (n=0~m-1, m+1~15)
becomes 10'. On the other hand, in the encoder 2, the transistor J (2 or 1) of the logic block 2-m, which receives the output line Sm which is "1n" among the output lines Sn of the preceding one detection circuit 1, is turned on, and the output line E.-E, information indicating the number of ic shift bits is output. (However, Eo
, E always outputs the sum of 101) Next, the normalization of binary coded decimal numbers will be explained using a specific example. As shown in FIG. 4, consider 4-digit (16-bit) binary-coded decimal floating-point data. The above data is 0 in decimal
．． 293, which is expressed as X in binary coded decimal notation. From 5DII+ in data X, D14 e
D13 and the first one to become u3pr is Do, so in the preceding one detection circuit 1 of FIG. The output line S.-8,ll of the preceding one detection circuit l
? In the manually operated encoder 2, only the transistor Qll of the logic block 2-9, which inputs %Sll, is turned on.
Output line E3 becomes 0'', but %at remains charged to 11''. Furthermore, in shifter 3, the number of shift bits when S is 61'' is 4 according to the truth table in Figure 6.
Therefore, the data X? Take it as input, actually shift it by 4 bits, and get data Y? obtain. So far logical block 1
-15 to 1-0 have all been described as having the same configuration, but since the final stage logic block l-0 does not have a next stage logic block, there is no means for transmitting the zero transmission signal Bo to the next stage. It is not necessary to have a switch transistor Roe, which is omitted in the embodiment of FIG.

With the configuration described above, the preceding one detection circuit 1 is able to detect the number closest to the MSB, including the MSB, and the encoder 2 is able to detect all the information on the number of shift bits necessary for normalization. In the above embodiment, 4-digit (16-bit) data has been explained, but 8-digit (32-bit) data can be output as a base number code.
% 16 digits (64 pits)... The larger the bit width, the faster normalization becomes possible compared to conventional binary coded decimal normalization processing.

Next, we will explain the second embodiment in which binary numbers can be normalized at the same time.
As shown in the figure. The block diagram of the second embodiment is also the same as that in FIG. The preceding one detection circuit 1 is exactly the same as the first embodiment shown in FIG.
According to the ff signal V, a shift operation is actually performed. The second embodiment differs from the first embodiment in the encoder 2. In the first embodiment, %Eo and El of the output of the encoder 2 are always outputted as '0#, but in this embodiment, as shown in FIG. ”
When MC is recharged to "1" and φ1 changes to @0, the encoder 2 inputs the active output line S□ from the preceding one detection circuit 1 [7" lock 2-r
Turn on all transistors Qj (4 to 1) in n and set the number of shift bits required for binary normalization to E. -E, is converted into a binary uncle code and sent to the shifter 3. The position of the transistor of encoder 2 in FIG.
The number of bits shifted by the shifter is shown in FIG. By configuring the encoder 20 part as shown in Figure 5,
Normalization of binary numbers can also be realized at high speed with relatively little hardware, but in this embodiment, by controlling the output lines E0 and E of the encoder 2 with the control signal BCD/BIN, the normalization of binary numbers, Normalization of both binary coded IO base numbers can be realized at high speed with the same hardware.Next, the second embodiment shown in FIG. 5 will be explained in detail. Now, let the data to be normalized be 16 and cut data, and 0000001
Consider binary data 010010011. Considering the data Th2 evolution lO base number, 0293 (10
).

First, when normalizing the data as a binary number, the control signal BCD/BIN is set to "0#".As explained in the first embodiment, when the data is input, the output of the preceding one detection circuit is Of 80 to 5IIl, only S becomes active, and all the transistors Qj in the logic block 2-9 of encoder 2, which are input to S, ?, are turned on, but since the control signal BCD/BIN is 10'',
Transistor Tr3 is off and encoder 2 output E, ~
E0 is directly inputted to the shifter 3 as information on the number of shift bits, and according to the truth table in FIG.
Normalized data 7 of 000 is obtained. Next, when normalizing the data tube as a binary coded decimal number, the control signal BCD
/BIN is set to 11". As in the case of binary number normalization, all the transistors Qj in the logic block 2-9 of the encoder 2 are turned on, and the output line E of the encoder 2 is turned on.
, ~E0 outputs the same shift bit number information as in the case of binary normalization, but the control signal BCD/BIN is “
1", the transistor Tr3 is turned on, and the output lines E., E, are forcibly set to "0#," and the information on the corrected shift bit number in units of 4 bits is input to the shifter 3. According to the truth table in Figure 9, the input data is
Bit shift to 0010100100110000 (
2930) is obtained.

As described above, in the second embodiment, by adding a simple control circuit to the output line of the encoder 2, normalization of binary numbers and binary coded decimal numbers can be realized at high speed with less hardware. As mentioned above, normalization processing is indispensable in floating-point calculations, and its weight in the entire floating-point calculations is large. Therefore, by using the second embodiment, floating point operations of binary numbers and binary coded decimal numbers can be processed at high speed with less hardware.

[Brief explanation of the drawing]

FIG. 1 is a binary and binary coded decimal floating point format, FIG. 2 is a block diagram of the normalization processing process, and FIG. 3 is a preceding detection in the first embodiment of the normalization circuit according to the present invention. FIG. 4 is a block diagram showing the normalization processing process when the mantissa is specifically set to 0293, and FIG. 5 is a circuit diagram of the circuit and encoder, and FIG. FIG. 3 is a circuit diagram of an encoder. FIG. 6 is a truth table of the first detection circuit and the encoder in the first embodiment, FIG. 7 is a layout table of gate transistors of the encoder in the first embodiment, and FIG. 8 is a diagram of the encoder in the second embodiment. The encoder gate transistor layout table, Figure 9, is as follows:
2nd embodiment Preceding one detection circuit in V and encoder A
...Encoder, 3...C7ri, 4+f
vln...NOR game), Nn...Inverter, 'l'rlTr:IQ m...Discharge transistor, 'l'r2+Pn...
- Grichi y-ditransistor sRn...Switch transistor (n=0.1.2 to 15).

Claims (1)

[Claims] Data expressed in binary coded 1O base is input, and the most significant bit of the data is 1? an encoder that converts into shift information in predetermined bit units based on the output information from the preceding one detection circuit; and a shifter that shifts the input data according to shift information of the encoder.