JPS5690343A - Data normalization device - Google Patents

Data normalization device

Info

Publication number
JPS5690343A
JPS5690343A JP16902079A JP16902079A JPS5690343A JP S5690343 A JPS5690343 A JP S5690343A JP 16902079 A JP16902079 A JP 16902079A JP 16902079 A JP16902079 A JP 16902079A JP S5690343 A JPS5690343 A JP S5690343A
Authority
JP
Japan
Prior art keywords
shift amount
data
mantissa
circuit
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16902079A
Other languages
Japanese (ja)
Inventor
Shigemi Uemoto
Koichi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16902079A priority Critical patent/JPS5690343A/en
Publication of JPS5690343A publication Critical patent/JPS5690343A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To execute data normalization processing by 1 machine cycle, by deriving the shift amount of a mantissa data, shifting the mantissa data by the shift amount, and at the same time, adding this shift amount to an exponential part data.
CONSTITUTION: The detection circuit 3 detects the mantissa sign and fraction overflow of the mantissa input data retained in the register 1. The detection circuit 4 detects whether each 4 bits after 8 bit of the mantissa data are all "0" or all "1". The output of both the circuits 3, 4 are provided to the shift amount deciding circuit 5, by which the shift amount is decided. The adder 7 adds the shift amount decided by the circuit 5 to the exponential input data retained in the register 2. As a result of this addition, the exponent overflow and the exponent underflow are detected by the detection circuit 8. On the other hand, the shifting circuit 6 decodes the shift amount of the circuit 5, shifts the input mantissa data, and a normalized data is generated in the register 9 by combining said output bit and the output bit of the adder 7.
COPYRIGHT: (C)1981,JPO&Japio
JP16902079A 1979-12-25 1979-12-25 Data normalization device Pending JPS5690343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16902079A JPS5690343A (en) 1979-12-25 1979-12-25 Data normalization device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16902079A JPS5690343A (en) 1979-12-25 1979-12-25 Data normalization device

Publications (1)

Publication Number Publication Date
JPS5690343A true JPS5690343A (en) 1981-07-22

Family

ID=15878834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16902079A Pending JPS5690343A (en) 1979-12-25 1979-12-25 Data normalization device

Country Status (1)

Country Link
JP (1) JPS5690343A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083139A (en) * 1983-10-13 1985-05-11 Nec Corp Normalizing circuit of binary-coded decimal number
JPS63123123A (en) * 1986-11-12 1988-05-26 Nec Corp Unnormalized floating point arithmetic unit
JPS6448125A (en) * 1987-08-18 1989-02-22 Nec Corp Normalization requesting circuit for floating-point arithmetic operation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083139A (en) * 1983-10-13 1985-05-11 Nec Corp Normalizing circuit of binary-coded decimal number
JPH0366692B2 (en) * 1983-10-13 1991-10-18 Nippon Electric Co
JPS63123123A (en) * 1986-11-12 1988-05-26 Nec Corp Unnormalized floating point arithmetic unit
JPS6448125A (en) * 1987-08-18 1989-02-22 Nec Corp Normalization requesting circuit for floating-point arithmetic operation

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