JPS5599648A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5599648A
JPS5599648A JP687279A JP687279A JPS5599648A JP S5599648 A JPS5599648 A JP S5599648A JP 687279 A JP687279 A JP 687279A JP 687279 A JP687279 A JP 687279A JP S5599648 A JPS5599648 A JP S5599648A
Authority
JP
Japan
Prior art keywords
carry
adder
ahead
look
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP687279A
Other languages
Japanese (ja)
Inventor
Tsutomu Sakamoto
Kazutoshi Eguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP687279A priority Critical patent/JPS5599648A/en
Publication of JPS5599648A publication Critical patent/JPS5599648A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate the redundant areas for the arithmetic circuit by selecting the carry to be supplied to the adder via the selector.
CONSTITUTION: In the case of the operation for the fixed decimal point, address 1W6 function as the full carry look-ahead high-speed adder/subtractor of 32 bits each via high-speed look-ahead carry generators 7W9. While in the case of the operation for the floating decimal point, data selector 10 selects either one of the carry sent from high-speed look-ahead carry generator 7 and the carry from adder 2 and then applies it to adder 1. At the same time, data selector 11 selects one of the carry from generator 7 and the input given from other generator to supply it to adder 2. Accordingly, adders 1 and 2 carry out the operation of the exponent part as the 8-bit adder; while adders 3W6 perform the operation of the mantissa part as the 24-bit full carry look-ahead high-speed adder respectively.
COPYRIGHT: (C)1980,JPO&Japio
JP687279A 1979-01-24 1979-01-24 Data processor Pending JPS5599648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP687279A JPS5599648A (en) 1979-01-24 1979-01-24 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP687279A JPS5599648A (en) 1979-01-24 1979-01-24 Data processor

Publications (1)

Publication Number Publication Date
JPS5599648A true JPS5599648A (en) 1980-07-29

Family

ID=11650313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP687279A Pending JPS5599648A (en) 1979-01-24 1979-01-24 Data processor

Country Status (1)

Country Link
JP (1) JPS5599648A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10488753B2 (en) 2015-09-08 2019-11-26 Canon Kabushiki Kaisha Substrate pretreatment and etch uniformity in nanoimprint lithography
US10509313B2 (en) 2016-06-28 2019-12-17 Canon Kabushiki Kaisha Imprint resist with fluorinated photoinitiator and substrate pretreatment for reducing fill time in nanoimprint lithography

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155027A (en) * 1976-06-18 1977-12-23 Fujitsu Ltd Multi-input adder for single-width data and double-width data

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155027A (en) * 1976-06-18 1977-12-23 Fujitsu Ltd Multi-input adder for single-width data and double-width data

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10488753B2 (en) 2015-09-08 2019-11-26 Canon Kabushiki Kaisha Substrate pretreatment and etch uniformity in nanoimprint lithography
US10509313B2 (en) 2016-06-28 2019-12-17 Canon Kabushiki Kaisha Imprint resist with fluorinated photoinitiator and substrate pretreatment for reducing fill time in nanoimprint lithography

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