JPS55121565A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS55121565A
JPS55121565A JP2948779A JP2948779A JPS55121565A JP S55121565 A JPS55121565 A JP S55121565A JP 2948779 A JP2948779 A JP 2948779A JP 2948779 A JP2948779 A JP 2948779A JP S55121565 A JPS55121565 A JP S55121565A
Authority
JP
Japan
Prior art keywords
multiplication
routine
calculation
summing
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2948779A
Other languages
Japanese (ja)
Other versions
JPS619658B2 (en
Inventor
Shintaro Hashimoto
Shigeaki Masuzawa
Kosuke Nishimura
Hisao Kunida
Tomohiro Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2948779A priority Critical patent/JPS55121565A/en
Priority to DE3009692A priority patent/DE3009692C2/en
Publication of JPS55121565A publication Critical patent/JPS55121565A/en
Priority to US06/353,092 priority patent/US4707794A/en
Publication of JPS619658B2 publication Critical patent/JPS619658B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To enable efficient totalizing calculation by informing an operator that the number of times of summing up is ineffective when any other key than a steady calculation key is operated.
CONSTITUTION: Four arithmetic routines described hereafter are available. The (1) multiplication routine (m1→m2→m6→m7→m8) provides usual multiplication or continuous calculation. The (2) routine attains the inhibition of the number of times of summing up in totalization mode. The (3) routine gives effect to constant-angle multiplication in totalization mode. Then, the (4) routine performs steady multiplication in nontotalization mode. Through those flows, it is informed that at least while the key for the steady calculation is not operated in totalization mode, the number of times of summing up in ineffective. As for the imformating method, audio output circuit CVV outputs data stored in registers X and GT by sound via arithmetic circuit Cu.
COPYRIGHT: (C)1980,JPO&Japio
JP2948779A 1979-03-13 1979-03-13 Electronic computer Granted JPS55121565A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2948779A JPS55121565A (en) 1979-03-13 1979-03-13 Electronic computer
DE3009692A DE3009692C2 (en) 1979-03-13 1980-03-13 Electronic calculator with acoustic data output
US06/353,092 US4707794A (en) 1979-03-13 1982-03-01 Playback operation circuit in synthetic-speech calculator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2948779A JPS55121565A (en) 1979-03-13 1979-03-13 Electronic computer

Publications (2)

Publication Number Publication Date
JPS55121565A true JPS55121565A (en) 1980-09-18
JPS619658B2 JPS619658B2 (en) 1986-03-25

Family

ID=12277425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2948779A Granted JPS55121565A (en) 1979-03-13 1979-03-13 Electronic computer

Country Status (1)

Country Link
JP (1) JPS55121565A (en)

Also Published As

Publication number Publication date
JPS619658B2 (en) 1986-03-25

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