JPS5379338A - Multiplication system - Google Patents
Multiplication systemInfo
- Publication number
- JPS5379338A JPS5379338A JP15496076A JP15496076A JPS5379338A JP S5379338 A JPS5379338 A JP S5379338A JP 15496076 A JP15496076 A JP 15496076A JP 15496076 A JP15496076 A JP 15496076A JP S5379338 A JPS5379338 A JP S5379338A
- Authority
- JP
- Japan
- Prior art keywords
- multiplication system
- expressed
- improving
- computer
- maximum value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To operate negative maximum value 2m-which can be expressed by operation bit width m of the computer-by improving the logical equipment of the multiplier circuit due to Boolean method when the multiplication processing is performed by using an arithmetic operation circuit.
COPYRIGHT: (C)1978,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15496076A JPS5379338A (en) | 1976-12-24 | 1976-12-24 | Multiplication system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15496076A JPS5379338A (en) | 1976-12-24 | 1976-12-24 | Multiplication system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5379338A true JPS5379338A (en) | 1978-07-13 |
Family
ID=15595657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15496076A Pending JPS5379338A (en) | 1976-12-24 | 1976-12-24 | Multiplication system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5379338A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63292324A (en) * | 1987-05-11 | 1988-11-29 | ユナイテツド テクノロジーズ コーポレーション | Binary multiplier circuit |
-
1976
- 1976-12-24 JP JP15496076A patent/JPS5379338A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63292324A (en) * | 1987-05-11 | 1988-11-29 | ユナイテツド テクノロジーズ コーポレーション | Binary multiplier circuit |
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