JPS55110343A - Arithmetic circuit - Google Patents

Arithmetic circuit

Info

Publication number
JPS55110343A
JPS55110343A JP1820279A JP1820279A JPS55110343A JP S55110343 A JPS55110343 A JP S55110343A JP 1820279 A JP1820279 A JP 1820279A JP 1820279 A JP1820279 A JP 1820279A JP S55110343 A JPS55110343 A JP S55110343A
Authority
JP
Japan
Prior art keywords
digit
hardware
counter
shift register
scale
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1820279A
Other languages
Japanese (ja)
Inventor
Hiroyasu Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1820279A priority Critical patent/JPS55110343A/en
Publication of JPS55110343A publication Critical patent/JPS55110343A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the scale of hardware for a value comparison and memory storage by giving effect to digit-number compression of a multi-digit arithmetic result through floating conversion.
CONSTITUTION: Product and sum arithmetic results of inputs A1 and B1 obtained through the multiplication of multiplication of multiplier circuit 1 and addition of adder circuit 2 are stored as multi-digit data in shift register 3. This shift register 3 is shifted by clock pulses, which are counted by exponent counter 4 to stop the supply of clock pulses by the carry signal output of counter 4, and digit-number data is obtained by converting which has the output of this counter at an exponent part and fixed high-order bits of shift register 3 at a mantissa part. This conversion output is stored in memory 7 and compared. The hardware, even if on small scale, can display a function equivalent to that of large-scale hardware.
COPYRIGHT: (C)1980,JPO&Japio
JP1820279A 1979-02-19 1979-02-19 Arithmetic circuit Pending JPS55110343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1820279A JPS55110343A (en) 1979-02-19 1979-02-19 Arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1820279A JPS55110343A (en) 1979-02-19 1979-02-19 Arithmetic circuit

Publications (1)

Publication Number Publication Date
JPS55110343A true JPS55110343A (en) 1980-08-25

Family

ID=11965045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1820279A Pending JPS55110343A (en) 1979-02-19 1979-02-19 Arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS55110343A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5325316A (en) * 1990-10-11 1994-06-28 Fujitsu Limited Compression processing method of real number data in processing system and apparatus therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5325316A (en) * 1990-10-11 1994-06-28 Fujitsu Limited Compression processing method of real number data in processing system and apparatus therefor

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