JPS61246837A - Parallel multiplier - Google Patents

Parallel multiplier

Info

Publication number
JPS61246837A
JPS61246837A JP60087741A JP8774185A JPS61246837A JP S61246837 A JPS61246837 A JP S61246837A JP 60087741 A JP60087741 A JP 60087741A JP 8774185 A JP8774185 A JP 8774185A JP S61246837 A JPS61246837 A JP S61246837A
Authority
JP
Japan
Prior art keywords
data
adder
addition
partial products
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60087741A
Other languages
Japanese (ja)
Inventor
Shigeru Tanaka
茂 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60087741A priority Critical patent/JPS61246837A/en
Publication of JPS61246837A publication Critical patent/JPS61246837A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To obtain a high-speed parallel multiplier suitable for circuit integration with high regularity by using the Booth algorithm and performing addition of n/2-set of partial product in parallel and giving the result to a full adder. CONSTITUTION:A data in 26-bit being the sum of two sets of partial products is outputted from each of the 1st-4th arithmetic blocks 11-14. Then the full adder 15 is arranged two-dimensionally from the 1st stage to the 4th stage, and the data of 26 bits being the sum of the partial products outputted from the arithmetic block of the corresponding stage, the sum output data of the full adder 15 of the high-order stage and the carry output data are fed as the input data to each full adder 15 to apply addition. Then the final addition is conducted by an adder 17 to execute multiplication.

Description

【発明の詳細な説明】 ［＋発明の技術分野〕 この発明は集積回路で実現するのに適したディジタルの
並列乗算器に関する。DETAILED DESCRIPTION OF THE INVENTION [+Technical Field of the Invention] The present invention relates to a digital parallel multiplier suitable for implementation in an integrated circuit.

［発明の技術的背景とその問題点］ ディジタルの乗算を高速で実行する方式として、乗数、
被乗数から生成される部分積を多数の全加算器を使用し
て加算する並列乗算方式がよく知られている。この並列
乗算方式における演算の高速化に有効な手段として、加
算の方式を工夫することにより加算の段数を減少させる
ことが考えられる。部分積の数を減少させて部分積の加
算段数を減少させる方式には従来からよく知られている
クラス（Ｗａ　Ｉ　ｌ　ａｃｅ＞のトリーという方式が
あり、この方式を採用すれば通常の全加算器をアレイ状
に配列する方式に比較して、加算段数を大幅に減少させ
ることができる。しかし、ワラスの方式による加算では
乗算器の構成が規則的でなくなるため、集積回路化の際
の設計に多大の手間と時間を必要とする欠点がある。こ
のため、集積回路化に適した規則性の高い構成であり、
かつ高速な並列乗算器が求められている。[Technical background of the invention and its problems] Multipliers,
A parallel multiplication method in which partial products generated from multiplicands are added using a large number of full adders is well known. As an effective means for speeding up calculations in this parallel multiplication method, it is conceivable to reduce the number of addition stages by devising an addition method. There is a well-known class of methods (Wa I l ace> tree method) that reduces the number of partial product addition stages by reducing the number of partial products. Compared to the method of arranging multipliers in an array, the number of addition stages can be significantly reduced. However, with addition using the Wallas method, the multiplier configuration is not regular, so it is difficult to design when integrating the multipliers. The drawback is that it requires a lot of effort and time.For this reason, it has a highly regular configuration suitable for integrated circuits.
There is a need for a high-speed parallel multiplier.

［発明の目的〕 この発明は上記のような事情を考慮してなされたもので
ありその目的は、集積回路化に適した規則性の高い構成
であり、かつ高速な並列乗算器を提供することにある。[Object of the Invention] This invention has been made in consideration of the above circumstances, and its purpose is to provide a high-speed parallel multiplier with a highly regular configuration suitable for integrated circuits. It is in.

［発明の概要１ 高速に乗算を実行するための方法として知られているブ
ース（３ｏｏｔｈ）のアルゴリズムは、ｎｘｎビットの
乗算を行なう際に生成される部分積の数をｎ／２とする
ことができ、高速化に有効であることが知られている。[Summary of the invention 1 The Booth algorithm, which is known as a method for performing multiplication at high speed, can set the number of partial products generated when performing nxn bit multiplication to n/2. It is known to be effective in increasing speed.

そこでこの発明ではこのブースのアルゴリズムを用いて
、ｎｘｎビットの乗算を行なう際に生成されるｎ／２組
の部分積の加算を並列に実行し、これらの加算結果をア
レイ状に配列した３人力２出力の全加算器の一つの入力
として供給し、他の全加算器の入力として対応する他の
全加算器の出力を供給するように構成している。Therefore, in this invention, using Booth's algorithm, the addition of n/2 sets of partial products generated when performing nxn bit multiplication is executed in parallel, and the results of these additions are arranged in an array. The configuration is such that it is supplied as one input of a two-output full adder, and the corresponding output of the other full adder is supplied as the input of the other full adder.

［発明の実施例］ １以下、図面を参照してこの発明の一実施例を説明する
。[Embodiment of the Invention] One embodiment of the invention will be described below with reference to the drawings.

第１図はこの発明に係る並列乗算器を、被乗数が×１・
・・ｘ１６からなる１６ビツト、乗数がｙｌ・・・ｙ１
６からなる１６ビツトの１６ビツト×１６ビツトの乗算
を行なうものに実施した場合の回路構成を示すブロック
図である。この実施例回路ではまず、第２因に示すよう
に、ブースのアルゴリズムに従って、被乗数×１・・・
ｘ１６、乗数ｙ１・・・ｙ１６からａｌ・・・ａ１γ、
ｂｌ・・・ｂｌ７、・・・ｈｌ・・・ｈｔｌからなるそ
れぞれ１７ビツトの８組の部分積Ｚ１・・・ｚ８を生成
する。そしてこれら８組の部分積ｚ１・・・Ｚ８のうち
任意の二組の組合わせに対してまず加算を実行する。こ
の実施例ではｚｌと７５、Ｚ２と２６、ｚ３とｚ７、Ｚ
４とＺ８というように、第に番目と第｛Ｋ＋　（８／２
））番目のものをＣＬＡ　（キャリー・ルック・アヘッ
ド）方式の加算器により加算するようにしている。FIG. 1 shows a parallel multiplier according to the present invention, where the multiplicand is
...16 bits consisting of x16, multiplier is yl...y1
FIG. 6 is a block diagram showing a circuit configuration when implemented in a device that performs 16-bit x 16-bit multiplication of 16 bits consisting of 6 bits. In this embodiment circuit, first, as shown in the second factor, according to Booth's algorithm, the multiplicand x 1...
x16, multiplier y1...y16 to al...a1γ,
Eight sets of partial products Z1...z8 of 17 bits each are generated, each consisting of bl...bl7,...hl...htl. First, addition is performed on any two combinations of these eight partial products z1...Z8. In this example, zl and 75, Z2 and 26, z3 and z7, and Z
4 and Z8, and so on, the th and the {K+ (8/2
)) is added by a CLA (carry look ahead) adder.

上記のような各二組の部分積の生成および部分積の加算
を実行するのが、第１図において符号１１ないし１４で
示される第１段目ないし第４段目の演算ブロックである
。上記第１段目の演算ブロック１１から出力される各ビ
ットデータは、アレイ状に配列された第１段目の複数の
各全加算器１５にそれぞれ入力データの一つとして供給
される。なお、演算ブロック１１から出力される最下位
ビットおよびその１ビツト上位のデータは２個の全加算
器１５で構成された２ビツトのＣＬＡ方式の加算器１６
に供給されている。上記第１段目の複数の全加算器１５
および加算器１６のうち下位１２ビツトまでのものには
他の入力データとして２の補数生成および符号ピットの
ためのＰｌ・・・Ｐｌ２からなる補正データが乗数に応
じて供給されている。上記第２段目の演算ブロック１２
から出力される各ビットデータは、アレイ状に配列され
た第２段目の複数の各全加算器１５にそれぞれ入力デー
タの一つとして供給される。この場合も演算ブロック１
２から出力される最下位ビットおよびその１ビツト上位
のデータは２個の全加算器１５で構成された２ビツトの
ＣＬＡ方式の加算器１６に供給されている。そしてこれ
ら第２１段目の複数の各全加算器１６および加算器１６
には他の入力データおよび桁上げデータとして上記第１
段目の対応する全加算器１５および加算器１６の和出力
データＳおよび桁上げ出力データＣが供給されている。The first to fourth stage calculation blocks designated by reference numerals 11 to 14 in FIG. 1 execute the generation of each of the two sets of partial products and the addition of the partial products as described above. Each bit data outputted from the first stage arithmetic block 11 is supplied as one piece of input data to each of the plurality of first stage full adders 15 arranged in an array. Note that the least significant bit output from the calculation block 11 and the data one bit above it are processed by a 2-bit CLA type adder 16 composed of two full adders 15.
is supplied to. A plurality of full adders 15 in the first stage
And correction data consisting of Pl...Pl2 for two's complement generation and code pits is supplied to the lower 12 bits of the adder 16 as other input data in accordance with the multiplier. The above second stage calculation block 12
Each bit data outputted from the adder is supplied as one piece of input data to each of the plurality of second-stage full adders 15 arranged in an array. In this case as well, calculation block 1
The least significant bit and the data one bit above it outputted from 2 are supplied to a 2-bit CLA type adder 16 composed of two full adders 15. And each of these 21st stage full adders 16 and adders 16
Input the above first data as other input data and carry data.
Sum output data S and carry output data C of the full adder 15 and adder 16 corresponding to the stage are supplied.

同様に第３段目以降の演算ブロック１３．１４から出力
される各ビットデータは、アレイ状に配列された第３段
目、第４段目の複数の各全加算器１５および加算器１６
にそれぞれ入力データの一つとして供給される。そして
これら第３段目、第４段目の複数の各全加算器１５およ
び加算器１６には他の入力データおよび桁上げデータと
して第２段目、第３段目の対応する全加算器１５および
加算器１６の和出力データおよび桁上げ出力データが供
給されている。そして第４段目の複数の各全加算器１５
の和出力データおよび加算出力データ、加算器１６の桁
上げ出力データのうち必要なデータがＣＬＡ方式の加算
器１７に供給されている。Similarly, each bit data output from the calculation blocks 13.
are each supplied as one of the input data. The plurality of full adders 15 and adders 16 in the third and fourth stages receive other input data and carry data from the corresponding full adders 15 in the second and third stages. Also, sum output data and carry output data of the adder 16 are supplied. and a plurality of full adders 15 in the fourth stage.
Necessary data among the sum output data, addition output data, and carry output data of the adder 16 is supplied to the CLA type adder 17.

第３図は上記演算ブロック１１ないし１４それぞれの具
体的構成を示す回路図である。図において２１．２２が
それぞれ一つの部分積７を生成する部分積生成部である
。この両部分積生成部２１．２２はそれぞれ１７個のデ
ータセレクタ２３で構成されている。上記部分積生成部
２１．２２内のそれぞれ１１個のデータセレクタ２３の
うち最下位ビットおよび最上位ビットのものを除くもの
には入力データとして被乗数×１・・・×１６のうちそ
れぞれビットの隣合った一対のビットデータが供給され
、最下位ビットには入力データとして最下位ビットの被
乗数×１のみが、最上位ビットには入力データとして最
上位ビットの被乗数Ｘ１６のみがそれぞれ供給されてい
る。そしてこの部分積生成部２１．２２で生成された二
組の部分積は加算器２４に供給され、ここで二組の部分
積の加算データが生成される。なお、この演算ブロック
では前記のように８組の部分積Ｚ１・・・ｚ８うち、第
に番目と第｛Ｋ＋　（８／２））番目のものを加算する
ために、二つの部分積生成部２１．２２で生成される部
分積データが必要なピット数だけずらされた状態で加算
器２４に供給されている。FIG. 3 is a circuit diagram showing a specific configuration of each of the calculation blocks 11 to 14. In the figure, reference numerals 21 and 22 indicate partial product generation units that generate one partial product 7, respectively. Each of the two partial product generators 21 and 22 is composed of 17 data selectors 23. Of the 11 data selectors 23 in each of the partial product generators 21 and 22, those excluding the least significant bit and the most significant bit receive input data as input data adjacent to each bit of the multiplicand×1...×16. A matched pair of bit data is supplied, and the least significant bit is supplied with only the multiplicand of the least significant bit x1 as input data, and the most significant bit is supplied with only the multiplicand of the most significant bit x16 as input data. The two sets of partial products generated by the partial product generators 21 and 22 are supplied to the adder 24, where summation data of the two sets of partial products is generated. In addition, in this calculation block, in order to add the th and {K+ (8/2))th of the 8 sets of partial products Z1...z8 as described above, two partial product generators are used. The partial product data generated in steps 21 and 22 is supplied to the adder 24 after being shifted by the required number of pits.

上記各データセレクタ２３には選択用のデータとして乗
数ｙ１・・・ｙ１６に基づいて生成されるそれぞれ複数
ビットからなるデータ８１、Ｓ２が供給されており、各
データセレクタ２３はこれらデータＳ１もしくはＳ２に
応じてｘｉ、ｘｉ−１、ｘｉ、ｘｉ−”ｌ、Ｑもしくは
１の固定値のいずれか一つを選択的に出力する。ここで
ブースのアルゴリズムに従った部分積とは、上記のよう
に被乗数をＸとしたときに生成される部分積がＸ、−Ｘ
、２ｘ、−２Ｘ、Ｏもしくは１のいずれかであることを
いう。Each of the data selectors 23 is supplied with data 81 and S2 each consisting of a plurality of bits generated based on the multipliers y1...y16 as selection data, and each data selector 23 selects these data S1 or S2. Accordingly, one of the fixed values of xi, xi-1, xi, xi-"l, Q, or 1 is selectively output. Here, the partial product according to Booth's algorithm is as described above. The partial product generated when the multiplicand is X is X, -X
, 2x, -2X, O or 1.

このような構成の並列乗算器では、第１段目ないし第４
段目の演算ブロック１１ないし１４それぞれからは前記
のような２組の部分積の和である２６ビツトのデータが
出力される。これに対応して全加算器１５を第１段目な
いし第４段目に２次元的に配置し、各全加算器１５の入
力データとして対応する段の演算ブロックから出力され
る部分積の和である２６ビツトのデータと上位段の全加
算器１５の和出力データおよび桁上げ出力データを供給
して加算を行ない、最終的な加算を加算器１７で行なう
ことにより乗算を実行している。In a parallel multiplier with such a configuration, the first to fourth stages
Each of the calculation blocks 11 to 14 in the third stage outputs 26-bit data, which is the sum of the two sets of partial products as described above. Corresponding to this, full adders 15 are arranged two-dimensionally in the first to fourth stages, and the sum of partial products output from the operation blocks of the corresponding stage is used as the input data of each full adder 15. The 26-bit data, the sum output data and the carry output data of the full adder 15 in the upper stage are supplied for addition, and the final addition is performed by the adder 17 to execute multiplication.

ここで上記のような１６ビツトｘＩＧビツトの乗算を例
にすれば、通常のブースのアルゴリズム用いた乗算器で
は、全加算器のデータ通過時間をＴ　（ＦＡ）　、最終
段のＣＬＡ加算に要する時間をＴ　（ＣＬＡ）とすれば
全体の乗算時間はおよそ８ｘＴ　（ＦＡ）＋Ｔ　（ＣＬ
Ａ）となるが、上記実施例によれば ４ｘＴ　（ＦＡ）＋Ｔ　（ＣＬＡＩ　）＋Ｔ　（ＣＬＡ
２＞となる。上記時間Ｔ　（ＣＬＡＩ　）、Ｔ　（ＣＬ
Ａ２）はそれぞれ第３図回路の加算器２４で要する加算
時間、第１図回路の加算器１７で要する加算時間である
。ここでＴ（ＣＬＡ）とＴ　（ＣＬＡｌ　）、Ｔ　（Ｃ
ＬＡ２）は同程度の時間であり、４ＸＴ　（ＦＡ）に比
較してＴ　（ＣＬＡｌ　）もしくはＴ　（ＣＬＡ２）は
十分短いので、従来に比較して演算の大幅な高速化が達
成できる。また、回路の規則性が高い構成なので集積回
路化する際の設計も容易に行なうことができる。Taking the above 16 bit x IG bit multiplication as an example, in a multiplier using the normal Booth algorithm, the data passing time of the full adder is T (FA), and the time required for CLA addition at the final stage is T (FA). If T (CLA), the total multiplication time is approximately 8xT (FA) + T (CL
A), but according to the above embodiment, 4xT (FA) + T (CLAI) + T (CLA
2>. The above times T (CLAI), T (CL
A2) is the addition time required by the adder 24 of the circuit shown in FIG. 3, and the addition time required by the adder 17 of the circuit shown in FIG. 1, respectively. Here, T(CLA), T(CLAl), T(C
LA2) takes about the same amount of time, and T (CLAl ) or T (CLA2) is sufficiently short compared to 4XT (FA), so it is possible to achieve a significant increase in calculation speed compared to the conventional method. Furthermore, since the circuit has a highly regular configuration, it is easy to design the integrated circuit.

また第１段目ないし第４段目の演算ブロック１１ないし
１４で加算する部分積の組合せを第に番目と第｛Ｋ＋　
（８／２））番目にしているので、部分積生成部２１．
２２で生成される部分積データを加算する加算器２４で
は２ビツト入力の加算を行なう部分のビット数を最小に
でき、これにより加算器２４自体の構成も簡単にするこ
とができる。In addition, the combination of partial products to be added in the calculation blocks 11 to 14 in the first to fourth stages is the th and {K+
(8/2)), the partial product generator 21.
In the adder 24 that adds the partial product data generated in the adder 22, the number of bits in the part where 2-bit inputs are added can be minimized, and the configuration of the adder 24 itself can be simplified.

第４図はこの発明の他の実施例の構成を示すブロック図
である。この実施例では前記のような２ビツトのＣＬＡ
方式の加算器１６を用いずに、全加算器１５を用いて桁
上げ出力データおよび和出力デ　　　　□−夕を上段か
ら下段に伝達するようにしたものである。FIG. 4 is a block diagram showing the configuration of another embodiment of the invention. In this embodiment, the 2-bit CLA as described above is used.
In this embodiment, the carry output data and the sum output data are transmitted from the upper stage to the lower stage using the full adder 15 without using the adder 16 of the system.

なお、この発明は上記実施例に限定されるものではなく
種々の変形が可能であることはいうまでもない。例えば
上記実施例ではこの発明を１６ビットメ１６ビツトの乗
算器に実施した場合について説明したが、任意のビット
数のものにも実施が可能であることはいうまでもない。It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above-mentioned embodiment, the case where the present invention is implemented in a 16-bit to 16-bit multiplier has been described, but it goes without saying that it can be implemented in a multiplier of any number of bits.

さらに全加算器１５の配列の仕方および接続方法につい
ても種々の変形が可能であることはいうまでもない。Furthermore, it goes without saying that various modifications can be made to the arrangement and connection method of the full adders 15.

［発明の効果］ 以上説明したようにこの発明によれば、集積回路化に適
した規則性の高い構成であり、かつ高速な並列乗算器を
提供することができる。[Effects of the Invention] As described above, according to the present invention, it is possible to provide a high-speed parallel multiplier that has a highly regular configuration suitable for integrated circuit implementation.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例の回路構成を示すブロック
図、第２図は上記実施例回路においてブースのアルゴリ
ズムに従って生成される部分積を示す図、第３図は上記
実施例回路の一部分を具体的に示す回路図、第４図はこ
の発明の他の実施例の回路構成を示すブロック図である
。 １１、１２．１３．１４・・・演算ブロック、１５・・
・全加算器、１６、１７・・・加算器、２１．２２・・
・部分積生成部、２３・・・データセレクタ、２４・・
・加算器、Ｚ・・・部分積。FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention, FIG. 2 is a diagram showing partial products generated according to Booth's algorithm in the circuit of the embodiment, and FIG. 3 is a part of the circuit of the embodiment. FIG. 4 is a block diagram showing the circuit configuration of another embodiment of the present invention. 11, 12.13.14... Arithmetic block, 15...
・Full adder, 16, 17... Adder, 21.22...
・Partial product generation unit, 23...Data selector, 24...
・Adder, Z...partial product.

Claims (4)

【特許請求の範囲】[Claims] （１）乗数および被乗数の値に応じて２組の部分積を生
成する部分積生成手段およびこの部分積を加算する加算
手段を備えた演算ブロックを乗数もしくは被乗数のビッ
ト数に応じた数だけ配置し、上記各演算ブロックの加算
出力を一つの加算入力とする全加算器を必要な数だけ配
列し、これら各全加算器の他の加算入力として他の演算
ブロックからの加算出力が供給される他の全加算器の桁
上げ出力および和出力を供給するように構成したことを
特徴とする並列乗算器。(1) Arithmetic blocks equipped with partial product generation means for generating two sets of partial products according to the values of the multiplier and multiplicand and addition means for adding the partial products are arranged in a number corresponding to the number of bits of the multiplier or multiplicand. Then, a necessary number of full adders are arranged, each of which uses the addition output of each of the above calculation blocks as one addition input, and the addition output from another calculation block is supplied as the other addition input of each of these full adders. A parallel multiplier characterized in that it is configured to supply the carry output and sum output of another full adder. （２）前記部分積生成手段がキャリー・ルック・アヘッ
ド方式を用いた加算器である特許請求の範囲第１項に記
載の並列乗算器。(2) The parallel multiplier according to claim 1, wherein the partial product generating means is an adder using a carry look ahead method. （３）前記部分積生成手段がブースのアルゴリズムに基
づいて部分積を生成するように構成される特許請求の範
囲第１項に記載の並列乗算器。(3) The parallel multiplier according to claim 1, wherein the partial product generating means is configured to generate partial products based on Booth's algorithm. （４）前記部分積の数がＮ（ただしＮは偶数）であると
き、前記演算ブロック内の加算手段で加算される二つの
部分積が第Ｋ番目と 第｛Ｋ＋（Ｎ／２）｝番目のものである特許請求の範囲
第１項に記載の並列乗算器。(4) When the number of partial products is N (however, N is an even number), the two partial products added by the adding means in the calculation block are the K-th and {K+(N/2)}-th A parallel multiplier according to claim 1, which is a parallel multiplier.
JP60087741A 1985-04-24 1985-04-24 Parallel multiplier Pending JPS61246837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60087741A JPS61246837A (en) 1985-04-24 1985-04-24 Parallel multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60087741A JPS61246837A (en) 1985-04-24 1985-04-24 Parallel multiplier

Publications (1)

Publication Number Publication Date
JPS61246837A true JPS61246837A (en) 1986-11-04

Family

ID=13923351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60087741A Pending JPS61246837A (en) 1985-04-24 1985-04-24 Parallel multiplier

Country Status (1)

Country Link
JP (1) JPS61246837A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477479A (en) * 1993-03-08 1995-12-19 Nkk Corporation Multiplying system having multi-stages for processing a digital signal based on the Booth's algorithm
KR960042334A (en) * 1995-05-15 1996-12-21 김주용 Parallel Independent Multibit Adder
CN107977191A (en) * 2016-10-21 2018-05-01 中国科学院微电子研究所 A kind of low power consumption parallel multiplier

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477479A (en) * 1993-03-08 1995-12-19 Nkk Corporation Multiplying system having multi-stages for processing a digital signal based on the Booth's algorithm
KR960042334A (en) * 1995-05-15 1996-12-21 김주용 Parallel Independent Multibit Adder
CN107977191A (en) * 2016-10-21 2018-05-01 中国科学院微电子研究所 A kind of low power consumption parallel multiplier
CN107977191B (en) * 2016-10-21 2021-07-27 中国科学院微电子研究所 Low-power-consumption parallel multiplier

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