JPS6158036A - Multiplier - Google Patents
MultiplierInfo
- Publication number
- JPS6158036A JPS6158036A JP59179638A JP17963884A JPS6158036A JP S6158036 A JPS6158036 A JP S6158036A JP 59179638 A JP59179638 A JP 59179638A JP 17963884 A JP17963884 A JP 17963884A JP S6158036 A JPS6158036 A JP S6158036A
- Authority
- JP
- Japan
- Prior art keywords
- output
- supplied
- sum
- carry
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
- G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、例えば画像処理などのように高速な信号処
理が必要とされるものに使用される乗算器に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multiplier used in applications that require high-speed signal processing, such as image processing.
乗算器の乗算方式としては従来から様々な方式が提案さ
れているが、人手で行なう乗算と全く同じ原理を用い、
これを／・−ドウエアで実現したのが並列乗算器である
。これは第３図に示すように、乗数ｙと被乗数Ｘとの各
ビット毎の部分積を生成するためのアンドゲート１１と
、その部分積ｘ’ｙ、同じ桁の前段の和出力Ｓ′、およ
び下の桁からの桁上げ信号Ｃ′を足し合わせ加算出力Ｓ
および桁上げ信号Ｃを得る全加算器１２とを１つの単位
回路（基本セル）１３とし、この基本セルを第４図に示
すようにアレイ状に配置したものである。第４図は４×
４ビツトの乗算器を示すもので、Ｘ工〜ｘ４は被乗数、
ｙ１〜ｙ４は乗数、１３．〜１３，６は基本セλ、１４
は４ビツトの加算器、８１〜Ｓ、は乗算出力である。こ
の方式は、部分積の生成および加算を並列に行なうため
に、高速な演算が可能である。Various methods have been proposed for multiplier multiplication methods, but using exactly the same principle as multiplication performed manually,
A parallel multiplier realizes this using hardware. As shown in FIG. 3, this consists of an AND gate 11 for generating a partial product for each bit of the multiplier y and the multiplicand X, the partial product x'y, the sum output S' of the previous stage of the same digit, and the carry signal C' from the lower digit and add the summation output S
and a full adder 12 for obtaining a carry signal C are made into one unit circuit (basic cell) 13, and this basic cell is arranged in an array as shown in FIG. Figure 4 is 4×
This shows a 4-bit multiplier, where X~x4 is the multiplicand,
y1 to y4 are multipliers, 13. ~13,6 is the basic set λ, 14
is a 4-bit adder, and 81 to S are multiplication outputs. This method enables high-speed calculations because partial product generation and addition are performed in parallel.
しかし、上記のような構成では、ｎＸｎビットの乗算器
を形成しようとすると、基本セルが２ｎ個必要となシ、
ハードウェア量が多くなる欠点がある。However, in the above configuration, when trying to form an nXn bit multiplier, 2n basic cells are required.
The disadvantage is that the amount of hardware increases.
ところで、一般に信号の伝播時間は通過するセルの段数
で決定されるため、この方式ではｎＸｎｋ”ットの乗算
器において、基本セルラｎ回通過する（ここではセル・
アレイのみで最終段の加算器１４は含まない）ことにな
る。従って、さらに高速化を望むならば、基本セルの通
過段数を減らせば良く、これは同時にハードウェア量の
低減にもつながる。このようなセルの通過段数を減らす
方式として、Ｗａｌｌａｃｅのトリーがある。この方式
によればセルの通過段数は大幅に削減され、よシ一層の
高速化が期待される。By the way, in general, the propagation time of a signal is determined by the number of stages of cells it passes through, so in this method, the basic cellular signal passes through n times in a multiplier of nXnk'' (here, the cell
(only the array does not include the final stage adder 14). Therefore, if further speeding up is desired, the number of stages through which the basic cells pass can be reduced, which also leads to a reduction in the amount of hardware. Wallace's tree is a method for reducing the number of stages through which a cell passes. According to this method, the number of stages through which cells pass can be significantly reduced, and even higher speeds are expected.
しかし、ＬＳＩ化を考えると、上記Ｗａ ｌ ｌ ａ
ｃ ｅのトリ一方式はその・ぐターン形状を矩形にまと
めることが難しく、大きな無効エリアを生ずるためチッ
プの有効利用という点からは不適である。However, considering LSI conversion, the above-mentioned Wal la
The three-way type of ce is difficult to organize into a rectangular shape and produces a large ineffective area, making it unsuitable from the point of view of effective chip utilization.
また、必要な配線も複雑であシ、配線遅延も無視できな
い等の欠点を有している。Further, the required wiring is complicated, and the wiring delay cannot be ignored.
この発明は上記のような事情に鑑みてなされたもので、
その目的とするところは、高速動作が可能で、しかもＬ
ＳＩ化に適した規則的なパターンを有し、高集積化でき
る乗算器を提供することである。This invention was made in view of the above circumstances,
The purpose is to enable high-speed operation and to
It is an object of the present invention to provide a multiplier that has a regular pattern suitable for SI implementation and can be highly integrated.
すなわち、この発明においては、上記の目的を達成する
ために、通過セルの段数の低減という点からＢｏｏｔｈ
アルゴリズムと、２系統の同じ桁の加算という２つの方
式を併用したもので、Ｂｏｏｔｈアルゴリズムを用いる
ことによって通過セルの段数を１／２に低減するととも
に、同じ桁の加算を複数の経路を用いることによって約
ＩＡに減らし、合計で通過セルの段数を約１／４に減ら
すことによって高速化を図っている。また、基本的には
並列乗算器であるので・ぞターンの規則性も維持してい
る。That is, in this invention, in order to achieve the above object, the Booth
It combines two methods: an algorithm and two systems of addition of the same digit.By using the Booth algorithm, the number of stages of passing cells is reduced to 1/2, and the addition of the same digit can be performed using multiple paths. The speed is increased by reducing the total number of stages of passing cells to about 1/4. Also, since it is basically a parallel multiplier, it maintains the regularity of turns.
以下、この発明の一実施例について図面を参照して説明
する。An embodiment of the present invention will be described below with reference to the drawings.
一般に、部分積の生成で最もよく用いられる手法として
Ｂｏｏｔｈのアルゴリズムがある。このアルコリズムは
２の補数の乗算が補正なしで実行できるという利点があ
る。今、例として２ビア）のＢｏ ｏ ｔｈをあげて説
明する。２の補数表示のとき、乗数Ｙは、
（ｙ は符号ビット、ｙｎ−１〜ｙｌは数値部）で表わ
される。上式（１）は次のように書き換えることができ
る。Generally, Booth's algorithm is the most commonly used method for generating partial products. This algorithm has the advantage that two's complement multiplication can be performed without correction. Now, as an example, the explanation will be given using ``Both'' (2 vias). In two's complement representation, the multiplier Y is expressed as (y is a sign bit, yn-1 to yl are numerical parts). The above equation (1) can be rewritten as follows.
従って、乗数Ｐ＝Ｘ−Ｙは、
・・・・・・（３）
となる。上記（３）において、（ｙ２ 、；＋ｙ２ ｉ
＋１−２／２件。）は１相続く３ビツト（ｙ２ｉＩｙ２
ｉ＋１１ｙ２＄＋２）の値に応じてｒＯＪ 、 ｒ±１
」、「±２」の値を取るので、部分積はそれによってＯ
１±Ｘ、±２Ｘのどれかを取ることになる。前式（３）
から明らかなよう釦、Ｂｏｏｔｈのアルゴリズムを用い
れば、部分積は通常の並列乗算器のｎ個に対して半分の
ｎ／２個で済む。Therefore, the multiplier P=X-Y is as follows: (3). In (3) above, (y2 ,;+y2 i
+1-2/2 items. ) is one consecutive 3 bits (y2iIy2
rOJ, r±1 depending on the value of i+11y2$+2)
”, takes the value of “±2”, so the partial product becomes O
Either 1±X or ±2X will be taken. The previous formula (3)
As is clear from the above, if the Button and Booth algorithms are used, only n/2 partial products will be needed, which is half of the n pieces of a normal parallel multiplier.
一方、部分積の加算の段数を減らす手法として、第５図
に示すように同じ桁の加算を２つの経路（例えば偶数段
と奇数段）で行ない、最終段でその両者を加え合わせる
ものがある。この方式によれば、ｎＸｎビットの乗算が
す＋２段で計算できることになシ、ワード”長が煙かい
場合には大きな効果は得られないが、ワード長が長くな
るに従って効果的である。第５図において、ａを付した
符号は奇数段、ｂを付した符号は偶数段を示している。On the other hand, as a method to reduce the number of stages of addition of partial products, as shown in Figure 5, there is a method in which addition of the same digit is performed in two paths (for example, an even number stage and an odd number stage), and both are added in the final stage. . According to this method, multiplication of nXn bits can be calculated in +2 stages, and although it is not very effective when the word length is long, it becomes more effective as the word length becomes longer. In FIG. 5, the symbols appended with a indicate odd-numbered stages, and the symbols appended with b indicate even-numbered stages.
例えは、基本セル１５ｍからの和出力Ｓは、次段の基本
セル１５ｂを飛び越して１６ｈへ、また、キャリーＣも
同様に１個飛び越して１８ｈへ供給される。一方、偶数
段でも同様に例えば１５ｂからの和出力Ｓは基本セル１
６ｂへ、キャリーＣは基本セル１８ｂへそれぞれ供給さ
れる。このように、偶数段と奇数段でそれぞれ別々に加
算を行ない、最後に両者を加え合わせる（図ではセル１
９〜２２を用いている）ため、余分に２段必要となるが
、ワード長が長くなるに従ってその影響は薄らぐ。For example, the sum output S from the basic cell 15m skips the next stage basic cell 15b and is supplied to 16h, and the carry C similarly skips one cell and is supplied to 18h. On the other hand, in the same way for even-numbered stages, for example, the sum output S from 15b is the basic cell 1
6b and carry C are supplied to the basic cell 18b, respectively. In this way, addition is performed separately in the even-numbered stages and odd-numbered stages, and finally the two are added together (in the figure, cell 1
9 to 22), two extra stages are required, but this effect diminishes as the word length increases.
この発明においては、ノサターンの規則性を維持しつつ
しかも高速化を実現するために、上述した２つの方式を
併用して乗算器を形成している。第１図はその構成を示
すもので８×８ビツトの乗算器を示している。この乗算
器は第２図に示すような基本セル２３によって構成され
る。In this invention, in order to achieve high speed while maintaining the regularity of the nosaturn, the above-mentioned two methods are used together to form a multiplier. FIG. 1 shows its configuration, and shows an 8×8 bit multiplier. This multiplier is constituted by basic cells 23 as shown in FIG.
すなわち、和入力Ｓｉｎ、キャリー人カｃｉｎおよび被
乗数Ｘが供給され、その和出力Ｓ。ｕｔおよびキャリー
出力Ｃ６ｕｔｔ−得る全加算器２４の被乗数Ｘ入力端に
は、排他的ノアゲート２５の出力が供給される。この排
他的ノアゲート２５の一方の入力端には、反転信号（−
２Ｘ 、 −Ｘ ） ＮＥＧＡが供給され、他方の入力
端にはノアｒ −） ２６の出力が供給される。このノ
アｆ −） ２６の入力端には、アンドグー） ２７１
１２７．の出力がそれぞれ供給される。アンドゲート
２２□の一方の入力端には被乗数Ｘが、他方の入力端に
はＸセレクト信号５ＥＬＸがそれぞれ供給される。また
、アンドゲート２７□の一方の入力端には被乗数Ｘを２
倍した信号２Ｘが、他方の入力端にはこの２Ｘのセレク
ト信号５ＥＬ２Ｘがそれぞれ供給されるようになってい
る。That is, a sum input Sin, a carry number cin, and a multiplicand X are supplied, and the sum output S. The output of the exclusive NOR gate 25 is supplied to the multiplicand X input terminal of the full adder 24 which obtains ut and the carry output C6utt-. One input terminal of this exclusive NOR gate 25 is connected to an inverted signal (-
2X, -X) NEGA is supplied, and the output of the Noah r-) 26 is supplied to the other input end. At the input end of this Noah f-) 26, there is ANDG) 271
127. outputs are provided respectively. The multiplicand X is supplied to one input terminal of the AND gate 22□, and the X selection signal 5ELX is supplied to the other input terminal. Also, one input terminal of the AND gate 27□ has the multiplicand
The multiplied signal 2X is supplied to the other input terminal, and the 2X select signal 5EL2X is supplied to the other input terminal.
このような基本セル２３は、第１図に示すようにマトリ
ックス状に配設される。マトリックス状に配置された基
本セル２３＠＋２３１ｓ＋２３□、 ＋ ２３３６およ
び２３１１ ｌ ２３８．．２３□６１２３３．には被
乗数Ｘ０が、基本セル２３８ 。Such basic cells 23 are arranged in a matrix as shown in FIG. Basic cells 23@+231s+23□, +2336 and 2311 l 238. arranged in a matrix. ．． 23□61233. The multiplicand X0 is the basic cell 238.
２ Ｊ１７ Ｔ ２３２＠ ＋ ２３３１１および２３
丁・２３，６゜２３２６ ＋ ４？３３４には被乗数
Ｘ、が、基本セル２３１ ＋ ２３１６ ＋ ２３□、
２３．、および２３６゜２３１！、２３□４１２３３
！には被乗数Ｘ２が、以下、同様にして基本セル２３□
〜２３．．２３．。2 J17 T 232@ + 23311 and 23
D・23,6゜2326 + 4?334 has a multiplicand X, but the basic cell 231 + 2316 + 23□,
23. , and 236°231! , 23□41233
! is the multiplicand X2, and in the same way, the basic cell 23
~23. ．． 23. .
〜２３１Ｂ ＋ ２３ＩＩ〜２３□４および２３２１１
〜２３３、には被乗数Ｘ、〜Ｘ７がそれぞれ供給される
。ここで、各基本セルの右側から入力された被乗数が第
２図における２Ｘに、左側から入力された被乗数がＸに
和尚している。なお、基本セル２３．．２３□。、２３
□、および２３□６には被乗数Ｘ、２Ｘとして被乗数Ｘ
７が供給さね２３、．２３□ＩＩ １２Ｊ２？ ｌ
２３３６の２Ｘとして接地電位ｖＳ８が供給される。~231B + 23II ~23□4 and 23211
~233, are supplied with multiplicands X and ~X7, respectively. Here, the multiplicand input from the right side of each basic cell corresponds to 2X in FIG. 2, and the multiplicand input from the left side corresponds to X. Note that the basic cell 23. ．． 23□. , 23
□, and 23□6 are multiplicands X, 2X is the multiplicand
7 supplies 23, . 23□II 12J2? l
The ground potential vS8 is supplied as 2X of 2336.
一方、乗数Ｙ０〜Ｙ７はそれぞれ、３ビツトが１組とし
てデコーダ２８．〜２８４に供給される。ずなわち、デ
コーダ２°８１には乗数Ｙ０゜Ｙｌと接地電位ｖｓ８が
、デコーダ２８□には乗数Ｙ１ 、Ｙ２ 、Ｙ、が、デ
コーダ２８３には乗数Ｙ３ 、Ｙ４ 、Ｙ、が、デコー
ダ２８４には乗数Ｙ、、Ｙ、、Ｙ、がそれぞれ供給され
る。そして、上記デコーダ２８□から出力される制御信
号（Ｘセレクト信号５ＥＬＸ 、 ２Ｘセレクト信号５
ＥＬ２Ｘ 、反転信号ＮＥＧＡ）はそれぞれ、基本セル
２３、〜２３゜に供給され、デコーダ２８□から出力さ
れる制御信号はそれぞれ基本セル２３．。On the other hand, each of the multipliers Y0 to Y7 is processed as a set of 3 bits by the decoder 28. ~284. That is, the decoder 2°81 receives the multiplier Y0°Yl and the ground potential vs8, the decoder 28□ receives the multipliers Y1, Y2, Y, and the decoder 283 receives the multipliers Y3, Y4, Y, and the decoder 284 receives the multipliers Y1, Y2, Y, are supplied with multipliers Y, , Y, , Y, respectively. Then, the control signals (X select signal 5ELX, 2X select signal 5
EL2X, inverted signal NEGA) are supplied to the basic cells 23, to 23°, respectively, and the control signals output from the decoder 28□ are respectively supplied to the basic cells 23. .
〜２３１８に、デコーダ２８３から出力される制御信号
はそれぞれ基本セル２３□、〜２３□７に、デコーダ２
８４から出力される制御信号はそれぞれ基本セル２３２
６〜２３３６に供給ちれる。また、上記基本セル２３□
〜２３１゜、２３□２〜２３１ｇ ＋ ２３２、＋ ２
３□２ ” ３２１！ ＋ ２３３０および２３３、
にはそれぞれ、和入力Ｓｉｏおよびキャリー人力Ｃ，ｎ
として接地電位ｖ８ｓが供給される。~2318, the control signal output from the decoder 283 is sent to the basic cells 23□, ~23□7, and the decoder 2
Each control signal output from 84 is sent to basic cell 232.
It will be supplied from 6 to 2336. In addition, the above basic cell 23□
~231°, 23□2~231g +232, +2
3□2 ” 321! + 2330 and 233,
have a sum input Sio and a carry human power C,n, respectively.
The ground potential v8s is supplied as the ground potential v8s.
上記基本セル２３１は符号ビットとして働くもので、接
地電位ｖｓｓおよび電源電位ＶＤＤが供給される。同様
に、基本セル２３１．．２３□。。The basic cell 231 functions as a code bit, and is supplied with the ground potential vss and the power supply potential VDD. Similarly, basic cell 231. ．． 23□. .
２３□、にも接地電位ｖｓｓおよび電源電位”ＤＤが供
給される。上記基本セル２３″１〜２３５の和出力は、
基本セル２３□、〜２３□７に供給される。The ground potential vss and the power supply potential "DD" are also supplied to 23□.The sum output of the basic cells 23"1 to 235 is:
It is supplied to the basic cells 23□ to 23□7.
これら基本セル２３□〜２３２７のキャリー人力として
は、接地電位ｖｓｓが供給される。上記基本セル２３６
〜２３．から得られる和出力は、桁上げ信号を生成する
ための多入力高速加算器２９に供給される。上記基本セ
ル２３１゜〜２３，４の和出力はそれぞれ基本セル２３
，２〜２３５．に供給され、基本セル２３．、〜２３２
．の出力はそれぞれ上記多入力高速加算器２９に供給さ
れる。The ground potential vss is supplied as the carry power for these basic cells 23□ to 2327. The above basic cell 236
~23. The resulting sum output is fed to a multi-input high speed adder 29 for generating a carry signal. The sum output of the above basic cells 231° to 23,4 is the basic cell 23, respectively.
, 2-235. is supplied to the basic cell 23. ,~232
．． The outputs of are respectively supplied to the multi-input high speed adder 29.
また、基本セル２３□のキャリー出力および和出力はそ
れぞれ、加算器３０１．３０□に供給され、基本セル２
３．。のキャリー出力および和出力はそれぞれ加算器３
０．．３０．に、基本セル２３□１のキャリー出力およ
び和出力はそれぞれ加算器３０３ ＋３０４に、基本セ
ル２３２２のキャリー出力および和出力は加算器３０４
。Further, the carry output and sum output of the basic cell 23□ are respectively supplied to adders 301.30□, and the basic cell 23□
3. . The carry output and sum output of are respectively added to adder 3.
0. ．． 30. The carry output and sum output of basic cell 23□1 are sent to adders 303+304, and the carry output and sum output of basic cell 2322 are sent to adder 304.
.
３０、に、基本セル２３□２のキャリー出力および和出
力は加算器’３０．＋、１０．にそれぞれ供給される。30, the carry output and sum output of the basic cell 23□2 are sent to the adder '30.30. +, 10. are supplied respectively.
上記基本セル２３□４のキャリー出力は加算器３０．へ
供給されるとともに、和出力は多入力高速加算器２９へ
供給され、基本セル２３□７のキャリー出力および和出
力はそれぞれ上記多入力高速加算器２９へ供給される・
基本セル２３□、の和出力は加算器３０７へ供給され、
基本セル２３□、〜２３３４の和出力は加算器３θ。The carry output of the basic cell 23□4 is sent to the adder 30. At the same time, the sum output is supplied to the multi-input high-speed adder 29, and the carry output and sum output of the basic cell 23□7 are respectively supplied to the multi-input high-speed adder 29.
The sum output of the basic cell 23□ is supplied to the adder 307,
The sum output of the basic cells 23□ and 2334 is an adder 3θ.
〜３０．へ、キャリー出力は加算器３０７〜３０．２へ
それぞれ供給される。さらに、基本セル２３３ｓのキャ
リー出力は加算器３０１３へ、和出力は多入力高速加算
器２９へ供給され、基本セル２３３６の和出力およびキ
ャリー出力は多入力高速加算器２９へそｎぞれ供給さ、
れる。上記加算器３０１〜３０６の和出力は上記加算器
３０８〜３０ユ、へ、キャリー出力は加算器３０７〜３
０□２へそれぞれ供給される。上記加算器３０７〜３０
．ｓの和出力およびキャリー出力はそれぞれ、例えばＣ
ＬＡ（Ｃａｒｒｙ Ｌｏｏｋ Ａｈｅａｄ）等から成り
最終和を求めるための高速加算器３ノに供給される。ま
た、上記多入力高速加算器２９のキャリー出力は上記加
算器３０１．と上記高速加算器３１へそれぞれ供給され
る。そして、多入力高速加算器２９から乗算出力２０〜
ｚ７を、高速加算器３１から乗算出力２．〜２１４をそ
れぞれ得るようにして成る。~30. and carry outputs are supplied to adders 307-30.2, respectively. Furthermore, the carry output of the basic cell 233s is supplied to the adder 3013, the sum output is supplied to the multi-input high-speed adder 29, and the sum output and carry output of the basic cell 2336 are supplied to the multi-input high-speed adder 29,
It will be done. The sum output of the adders 301-306 is sent to the adders 308-30, and the carry output is sent to the adders 307-3.
0□2 respectively. The above adders 307 to 30
．． The sum and carry outputs of s are each, for example, C
The signal is supplied to a high-speed adder 3 which consists of LA (carry look ahead) and the like and is used to obtain the final sum. Further, the carry output of the multi-input high-speed adder 29 is supplied to the adder 301. and the high-speed adder 31, respectively. Then, the multi-input high-speed adder 29 outputs the multiplication output 20~
z7 is multiplied by the high-speed adder 31 as the multiplication output 2. .about.214 are obtained, respectively.
次に、上記のような構成において動作を説明する。被乗
数Ｘ０〜Ｘ７が各基本セル２３□〜２３３６に供給され
るとともに、乗数Ｙ０〜Ｙ７がデコーダ２８□〜２８４
に供給されると、これらデコーダ２８□〜２８４によっ
て３ビツトの乗数データのデコードが行なわれ、これに
対応した制御信号（Ｘセレクト信号ＳｇＬＸ 、 ２
Ｘセレクト信号５ＥＬ２Ｘ 、反転信号ＮＥＧＡ ）が
各基本セル２３、〜２３，６に供給されてＯ２士Ｘ、±
２Ｘの選択が行なわれる。これによって、被乗数Ｘ０〜
Ｘ７と乗数Ｙ０〜Ｙ７との部分積が生成される。この部
分積は、奇数段および偶数駿毎に加算され、上記基本セ
ル２３．〜２３ ｇ ＋ ２３１５〜２３４Ｂ ＋
２３□４〜２３□ｔ ＋ ２３３５ 、２３３６の和出
力およびキャリー出力の少なくとも一方が選択的に多入
力高速加算器２９に供給され、基本セル２３８．〜２３
□４および２３□８〜２３３５の和出力およびキャリー
出力の少なくとも一方がそれぞれ加算器３０．〜３０１
３に選択的に供給され、奇数段と偶数段の部分積の和が
最終的に加算される。そして、これら加算器３０７〜３
Ｑユ、の和出力およびキャリー出力が高速加算器３Ｉに
よって加算される。ここで、高速加算器３１の入力（加
算器３０７〜３０８．の出力）が確定したときには、下
位の加算器からの桁上げ信号も確定していなければなら
ない。このため下位側ではセルの段数を増やし和出力と
キャリー出力とを２つに絞シ込むことはせずに、２系統
のセルから出力された和出力とキャリー出力とから桁上
げ信号を生成する多入力高速加算器２９を用い、全ての
基本セルを通過する間に上位への桁上げを確定させてい
る。Next, the operation in the above configuration will be explained. Multiplicands X0 to X7 are supplied to each basic cell 23□ to 2336, and multipliers Y0 to Y7 are supplied to decoders 28□ to 284.
, the 3-bit multiplier data is decoded by these decoders 28□ to 284, and the corresponding control signals (X select signals SgLX, 2
The X select signal 5EL2X and the inverted signal NEGA) are supplied to each basic cell 23, to 23, 6, and the O2 signal X, ±
A 2X selection is made. By this, the multiplicand X0~
A partial product of X7 and the multipliers Y0 to Y7 is generated. These partial products are added for each odd-numbered stage and even-numbered stage, and are added to the basic cell 23. ~23g + 2315~234B +
At least one of the sum output and carry output of 23□4 to 23□t + 2335 and 2336 is selectively supplied to the multi-input high-speed adder 29, and the basic cell 238. ~23
At least one of the sum output and carry output of □4 and 23□8 to 2335 is sent to the adder 30. ~301
3, and the sums of the partial products of the odd and even stages are finally added. And these adders 307 to 3
The sum output and carry output of QY are added by high speed adder 3I. Here, when the input of the high-speed adder 31 (the output of the adders 307 to 308.) is determined, the carry signal from the lower adder must also be determined. Therefore, on the lower side, instead of increasing the number of cell stages and narrowing down the sum output and carry output to two, a carry signal is generated from the sum output and carry output output from the two systems of cells. A multi-input high-speed adder 29 is used to determine the carry to the higher order while passing through all the basic cells.
このような構成によれば、下表に示すように通過セルの
段数を低減でき、これによって高速化を図れる。また、
並列型であるのでパターン構成する際の規則性を維持で
き、ＬＳＩ化にも好。According to such a configuration, the number of stages of passing cells can be reduced as shown in the table below, thereby increasing the speed. Also,
Since it is a parallel type, regularity can be maintained when configuring patterns, making it suitable for LSI implementation.
適なものである。It is suitable.
このように、低ワード長の場合にはＢｏｏｔｈ乗算器と
大きく変わらないが、ワード長が長くなるに従ってセル
の通過段数に大きな差が現われる。As described above, in the case of a low word length, there is no big difference from a Booth multiplier, but as the word length becomes longer, a large difference appears in the number of stages through which cells pass.
以上説明したようにこの発明によれば、高速動作が可能
で、しかもＬＳＩ化に適した規則的なパターンを有し、
高集積化できる乗算器が得られる。As explained above, according to the present invention, it is possible to operate at high speed, and has a regular pattern suitable for LSI implementation.
A multiplier that can be highly integrated is obtained.
第１図はこの発明の一実施例に係わる乗算器の構成図、
第２図は上記第１図における基本セルの構成図、第３図
は従来の並列乗算器の基本の構成図、第４図は上記第３
図の基本セルを用いて桐成した並列乗算器の構成図、第
５図は部分積の加算の段数を減らす手法を説明するだめ
の図である。
Ｘ ｏ％Ｘ ７−被乗数、Ｙ、−Ｙ、−・・乗数、２３
１〜２３，６・・・基本セル、２８．〜２８４・・・デ
コーダ、２９・・・多入力高速加算器、３０．〜３０□
３・・・加算器、３１・・・高速加算器、ｚ０〜Ｚ１４
・・・乗算出力、５ＥＬＸ・・・Ｘセレクト信号、５Ｅ
Ｌ２Ｘ・・・２Ｘセレクト信号、ＮＥＧＡ・・・反転信
号、２４・・・全加算器、２５・・・排他的ノアケ”−
ト、２６・・・ノアゲート、２７□ 、２７□・・・ア
ンドゲート、Ｓい・・・和入力、Ｃ・・・キャリー人力
、５ｏｕｔ・・・和出力、ｎ
Ｃｏｕｔ・・・キャリー出力。FIG. 1 is a configuration diagram of a multiplier according to an embodiment of the present invention;
Fig. 2 is a block diagram of the basic cell in Fig. 1 above, Fig. 3 is a basic block diagram of a conventional parallel multiplier, and Fig. 4 is a block diagram of the basic cell in Fig. 1 above.
FIG. 5 is a block diagram of a parallel multiplier constructed using the basic cell shown in FIG. 5, and is a diagram used to explain a method of reducing the number of stages of addition of partial products. X o%X 7-multiplicand, Y, -Y, -... multiplier, 23
1 to 23, 6... basic cell, 28. ~284...Decoder, 29...Multi-input high-speed adder, 30. ~30□
3... Adder, 31... High speed adder, z0 to Z14
...Multiply output, 5ELX...X select signal, 5E
L2X...2X select signal, NEGA...inverted signal, 24...full adder, 25...exclusive noake"-
G, 26...Noah gate, 27□, 27□...AND gate, S...sum input, C...carry human power, 5out...sum output, n Cout...carry output.
Claims (2)
て、乗数の相隣り合う３ビットのデータに基づいて部分
積を生成し、これら部分積の同じ桁の加算を複数の経路
で行ない、上記複数の経路によって求めた部分積の和の
加算を行なって出力を得る如く構成したことを特徴とす
る乗算器。(1) In a parallel multiplier in which basic cells are arranged in an array, partial products are generated based on adjacent 3-bit data of the multiplier, and addition of the same digits of these partial products is performed in multiple paths. A multiplier characterized in that it is configured to obtain an output by adding the sums of partial products obtained through a plurality of paths.
クト信号が供給される第１のアンドゲートと、被乗数を
２倍した信号およびこの２倍した信号のセレクト信号が
供給される第２のアンドゲートと、上記第１、第２のア
ンドゲートの出力が供給されるノアゲートと、このノア
ゲートの出力および反転信号が供給される排他的ノアゲ
ートと、この排他的ノアゲートの出力および和信号、キ
ャリー信号が供給され和出力およびキャリー出力を得る
全加算器とを具備したことを特徴とする特許請求の範囲
第１項記載の乗算器。(2) The basic cell includes a first AND gate to which a multiplicand and a selection signal of this multiplicand are supplied, and a second AND gate to which a signal obtained by doubling the multiplicand and a selection signal of this doubled signal are supplied. , a NOR gate to which the outputs of the first and second AND gates are supplied, an exclusive NOR gate to which the output of this NOR gate and an inverted signal are supplied, and an output of this exclusive NOR gate, a sum signal, and a carry signal are supplied. 2. The multiplier according to claim 1, further comprising a full adder for obtaining a sum output and a carry output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59179638A JPS6158036A (en) | 1984-08-29 | 1984-08-29 | Multiplier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59179638A JPS6158036A (en) | 1984-08-29 | 1984-08-29 | Multiplier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6158036A true JPS6158036A (en) | 1986-03-25 |
| JPH0326857B2 JPH0326857B2 (en) | 1991-04-12 |
Family
ID=16069263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59179638A Granted JPS6158036A (en) | 1984-08-29 | 1984-08-29 | Multiplier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6158036A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5060183A (en) * | 1987-11-19 | 1991-10-22 | Mitsubishi Denki Kabushiki Kaisha | Parallel multiplier circuit using matrices, including half and full adders |
| FR2662829A1 (en) * | 1990-05-31 | 1991-12-06 | Samsung Electronics Co Ltd | Parallel multiplier using a skip array and a modified Wallace tree |
| JP2010165179A (en) * | 2009-01-15 | 2010-07-29 | Hiroshima Univ | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856033A (en) * | 1981-09-29 | 1983-04-02 | Fujitsu Ltd | Multiplying circuit |
-
1984
- 1984-08-29 JP JP59179638A patent/JPS6158036A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856033A (en) * | 1981-09-29 | 1983-04-02 | Fujitsu Ltd | Multiplying circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5060183A (en) * | 1987-11-19 | 1991-10-22 | Mitsubishi Denki Kabushiki Kaisha | Parallel multiplier circuit using matrices, including half and full adders |
| FR2662829A1 (en) * | 1990-05-31 | 1991-12-06 | Samsung Electronics Co Ltd | Parallel multiplier using a skip array and a modified Wallace tree |
| JP2010165179A (en) * | 2009-01-15 | 2010-07-29 | Hiroshima Univ | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0326857B2 (en) | 1991-04-12 |
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