JPS5764864A - Digital arithmetic circuit - Google Patents

Digital arithmetic circuit

Info

Publication number
JPS5764864A
JPS5764864A JP14105080A JP14105080A JPS5764864A JP S5764864 A JPS5764864 A JP S5764864A JP 14105080 A JP14105080 A JP 14105080A JP 14105080 A JP14105080 A JP 14105080A JP S5764864 A JPS5764864 A JP S5764864A
Authority
JP
Japan
Prior art keywords
register
bits
supplied
value
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14105080A
Other languages
Japanese (ja)
Other versions
JPS612989B2 (en
Inventor
Hisao Ishizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14105080A priority Critical patent/JPS5764864A/en
Publication of JPS5764864A publication Critical patent/JPS5764864A/en
Publication of JPS612989B2 publication Critical patent/JPS612989B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation

Abstract

PURPOSE:To obtain a high degree of interpolation value through a simple constitution of arithmetic circuit, by dividing N times the residue obtained by giving a 1/N division to a numerical value B and then adding and subtracting the residue to and from the result obtained by giving an addition/subtraction of the quotient to and from a numerical value A. CONSTITUTION:The 1st data of an RAMI is fed into a register 4, and the next data is supplied to a 2-bit shifter 3. Then upper 2 bits are supplied to a register 5; and the upper one of the lower 2 bits is defined as (a) with the lower one diefined as (b) respectively. These bits (a) and (b) are set to a register 7. On the other hand, the data stored in the registers 4 and 5 are added to each other at an adder 8, and the 1st interpolation value is set at a register 6. The next interpolation value is set at the register 4, and the contents of the register 6 is shifted with the contents of the register 5 kept it is. Then an addition is carried out 4 times. After this, the next data of the RAMI is put into the register 5 to perform the same operation. The carry of the addition is selected by a multiplexer 9 so that the value (a), (b) and O are supplied for twice of 4 times and the rest one time respectively.
JP14105080A 1980-10-08 1980-10-08 Digital arithmetic circuit Granted JPS5764864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14105080A JPS5764864A (en) 1980-10-08 1980-10-08 Digital arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14105080A JPS5764864A (en) 1980-10-08 1980-10-08 Digital arithmetic circuit

Publications (2)

Publication Number Publication Date
JPS5764864A true JPS5764864A (en) 1982-04-20
JPS612989B2 JPS612989B2 (en) 1986-01-29

Family

ID=15283078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14105080A Granted JPS5764864A (en) 1980-10-08 1980-10-08 Digital arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS5764864A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5167018A (en) * 1986-09-24 1992-11-24 Daikin Industries, Ltd. Polygon-filling apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5167018A (en) * 1986-09-24 1992-11-24 Daikin Industries, Ltd. Polygon-filling apparatus

Also Published As

Publication number Publication date
JPS612989B2 (en) 1986-01-29

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