JPS57196351A - Floating point multiplying circuit - Google Patents

Floating point multiplying circuit

Info

Publication number
JPS57196351A
JPS57196351A JP56079561A JP7956181A JPS57196351A JP S57196351 A JPS57196351 A JP S57196351A JP 56079561 A JP56079561 A JP 56079561A JP 7956181 A JP7956181 A JP 7956181A JP S57196351 A JPS57196351 A JP S57196351A
Authority
JP
Japan
Prior art keywords
register
processing
executed
normalization
carry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56079561A
Other languages
Japanese (ja)
Inventor
Tsutomu Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56079561A priority Critical patent/JPS57196351A/en
Publication of JPS57196351A publication Critical patent/JPS57196351A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/487—Multiplying; Dividing
    • G06F7/4876—Multiplying
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49936—Normalisation mentioned as feature only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding

Abstract

PURPOSE:To remarkably shorten a necessary time for processing, by providing a function part for forecasting the generation of carry from an adder, and executing the processing of normalization and round-off in accordance with a deciding output result value of the function part. CONSTITUTION:A data of the product derived by multiplication of a mantissa is registered to an accumulator register 11 and an extended register 12. At first, processing of normalization is executed, and whether bits 0-3 of the register 11 are zero or not is discriminated. In case of zero, subsequently, whether lower digits than a bit 4 of the register 11 are all ''1'' or not is decided by a carry generation forecasting circuit 15 in accordance with whether an output signal CLHAD of the circuit 15 is true or false, and only when the signal CLHAD is false, the registers 11 and 12 are left bit-shifted, and the normalization is executed. Subsequently, in case of round-off, addition by which a bit ''0'' of the register 12 is set as a carry-in (CI) input is executed. In this way, the processing sequence is simplified, the processing is executed at a high speed, and also operation of the exponential part is simplified.
JP56079561A 1981-05-26 1981-05-26 Floating point multiplying circuit Pending JPS57196351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56079561A JPS57196351A (en) 1981-05-26 1981-05-26 Floating point multiplying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56079561A JPS57196351A (en) 1981-05-26 1981-05-26 Floating point multiplying circuit

Publications (1)

Publication Number Publication Date
JPS57196351A true JPS57196351A (en) 1982-12-02

Family

ID=13693416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56079561A Pending JPS57196351A (en) 1981-05-26 1981-05-26 Floating point multiplying circuit

Country Status (1)

Country Link
JP (1) JPS57196351A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61122750A (en) * 1984-11-20 1986-06-10 Matsushita Electric Ind Co Ltd Arithmetic unit
US4926369A (en) * 1988-10-07 1990-05-15 International Business Machines Corporation Leading 0/1 anticipator (LZA)
KR100438566B1 (en) * 1996-12-10 2004-08-09 엘지전자 주식회사 Circuit for processing rounding of continuous multiplication/addition operations generating decimal point on dsp

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61122750A (en) * 1984-11-20 1986-06-10 Matsushita Electric Ind Co Ltd Arithmetic unit
US4926369A (en) * 1988-10-07 1990-05-15 International Business Machines Corporation Leading 0/1 anticipator (LZA)
KR100438566B1 (en) * 1996-12-10 2004-08-09 엘지전자 주식회사 Circuit for processing rounding of continuous multiplication/addition operations generating decimal point on dsp

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