JPS59103148A - Multiplying circuit - Google Patents

Abstract

PURPOSE:To perform the multiplication beginning from the highest bit without increasing the hardware of an adder by carrying out the multiplication of blocks containing the lowest bits from the multiplication of blocks containing the highest bits. CONSTITUTION:A processor which performs an operation of the floating decimal point data is provided with a host computer 1, interface part 2 and an arithmetic unit 3 having a pipeline stage. Furthermore an FIFO register which selects and supplies the arithmetic result of the unit 3 is added together with a register file 4 having a U-port register, memory part 5, address arithmetic part 6 and a microprogram controller 7. The multiplication is started from the blocks containing the highest bits through the multiplication of the blocks containing the lowest bits. The result of multiplication of a partial multiplier is shifted to the right by the bit number equivalent to the block length by a shifter and supplied to one side of an adder. Thus the multiplication is possible beginning from the highest bit without increasing the hardware of the adder.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a multiplication circuit that divides data serving as a multiplicand and a multiplier into a plurality of blocks, performs multiplication for each block, and obtains a product by accumulating the multiplication results. . The multiplication circuit according to the present invention is used, for example, when performing multiplication of double-precision floating point data, and is used as a pipeline multiplication circuit that executes vector operations at high speed.

[Prior art]

When performing multiplication of double precision floating point data, it is known that the mantissa is divided into several blocks, multiplication is performed for each block, and the mantissa is multiplied by accumulating the multiplication results. In this case, conventionally, the multiplication of blocks including the least significant bits of the mantissa part is started.

Normally, double-precision floating point data is stored in a memory 17K, and is read out from the memory each time a multiplication is performed.

When performing block-by-block multiplication, it is necessary to read each block from memory, but normally the block containing the least significant bit is stored at a higher memory address than the block not containing the least significant bit. The block containing the least significant bit is read on the second access.

For this reason, when pipeline multiplication is performed, a gap occurs in the pipeline, making it impossible to execute the pipeline operation at high speed.

In addition, when the IEEE standard floating point format is adopted, when the exponent part is all 1's, the number must be regarded as a non-number and a special predetermined value must be output as the multiplication result, but the least significant bit If multiplication is started from the block containing the least significant bit, the exponent data will be read after the block containing the least significant bit has been multiplied, resulting in a delay in recognition of non-numbers and disturbances in pipeline operation. Ta.

[Purpose of the invention]

An object of the present invention is to provide a multiplication circuit that can perform multiplication starting from data of a block including the most significant bit when multiplicand and multiplier data are divided into a plurality of blocks and multiplied.

One object of the present invention is to provide a multiplication circuit that can perform multiplication from data of a block including the most significant bit and has a simple circuit configuration.

[Summary of the invention]

The multiplication circuit according to the present invention has a partial product multiplier that performs block-by-block multiplication, and an adder that takes the multiplication result of the partial product multiplier as one input and the accumulated multiplication result as the other input, Further, a shifter having a function of right-shifting the multiplication result of the partial product multiplier by the number of bits of the block length is provided, and the output of the shifter is applied to one input of the adder.

According to the present invention, when starting from multiplication between blocks including the most significant bit, performing multiplication between blocks including the least significant bit, and adding this multiplication result to the accumulated multiplication result, the shifter uses the partial product. The multiplication result of the multiplier is shifted to the right by the number of bits of the block length and applied to one input of the adder.

This allows multiplication from the block containing the most significant bit without increasing the hardware scale of the adder.

Embodiment FIG. 1 is a diagram showing the overall configuration of a processing device for performing arithmetic operations on floating point data to which the present invention is applied.

In Figure 1, l is the host computer (HO8T)
, 2-digit interface section, 3-digit operation unit, 4 is a register file, 5 is a memory section, 6 is an address operation section,
It is a 7-digit microprogram controller. Each of the units 3 to 6 is controlled by a microprogram controller 7.

The multiplication circuit according to the invention is used inside the arithmetic unit 3.

FIG. 2 shows the configuration of the arithmetic unit 3. In the figure,
10 is a four-stage pipeline stage 10-1 to 10-
32-bit multiplier circuit consisting of 4, 11 digits, 3 stages
A 64-pit addition circuit consisting of brine stages 11-1 to 11-3, 12 to 15 are buses, 12 is the right input of the addition circuit 11, 13 is the left input of the addition circuit 11, and 141d is the left input of the multiplication circuit 10. Right input, 111: Multiply! ￥−
The left input signal of time M10 is input. 16 is a data bus that outputs the result of multiplication or addition; 17 is an adder circuit output signal line; 18 is a multiplier circuit output signal line; 19 is an adder circuit 1
20 is a signal line that inputs the lower 32 bits of 1 to the left input of the adder 11, 20 is a signal line that inputs the upper 32 bits of the adder 11 to the left input of the adder 11, and 21 is the upper output of the multiplier 10. A signal line 22 inputs 32 bits to the right input of the adder circuit 11, and a signal line 22 inputs the lower 32 bits of the multiplier circuit 10 to the lower 32 pits of the right input of the adder circuit 11.

Input to the multiplier circuit 10 is carried out through a multiplier circuit output signal line 14 and a multiplier circuit pressure input signal line 15, and its output is as follows.
The signal is sent to the data bus 16 via the signal line 21 to the adder circuit right input signal line 12K, and via the signal line 18 to the register file 4.

When the multiplication is double precision multiplication, the configuration is such that the lower 32 bits of the calculation result can be directly input to the right input of the addition circuit 11 via the signal line 22.

The input to the adder circuit 11 is single-precision data, and upper 32-bit data when double-precision is input in two parts via the adder circuit right input signal line 12 and the adder circuit output signal line 13. It is done.

The output of the adder circuit 11 is sent to the data bus 16 or via the signal line 17 to the register file 4, and via the input signal line 20 to the adder circuit input signal line 13.

For double-precision arithmetic, the lower 32 bits of the output are connected to signal line 19.
The configuration is such that it can be directly input to the left input of the adder circuit 11 via. Adder circuit 11 is described in U.S. Patent No. 4,075,7.
This is a pipeline addition circuit as exemplified by 04.

The detailed structure of the multiplication circuit 10 according to the invention will be explained below.

FIG. 3 shows the configuration of the register file 4. In the figure, 30 is a selector that selects one of the adder circuit output 17 and the multiplier circuit output 18, and 31 is a read request signal (a
g), FIFO (Fi
rst-In, First-□ut) register, 3
2t-j: adder circuit output 17, multiplier circuit output 18, selector for selecting one of the data buses 16, 2 ports with 33 digits, two read addresses (RAI, RA2), and a write address (WA). It is a register.

Data is written into the FIFO 31 by selecting either the adder circuit output signal line 17 or the multiplier circuit output signal line 18 by the selector 30 and turning on the write request signal WE.

Further, reading from the FIFO 31 is performed by turning on the read request signal BE, which is output to the adding circuit input signal line 12 and the left input signal line 13.

The input to the 2-vote register 33 is written into the write address WA by selecting one of the adder circuit output signal line 17, the multiplier circuit output signal line 18, and the data bus 16 by the selector 32. Further, reading from the 2-boat register 33 is performed from the positions specified by the read addresses RAI, R, and A2 of the 2-boat register 33, and the multiplier circuit input signal line 15, adder circuit input signal line 13, It is output to the multiplier circuit output signal line 14 and the adder circuit input signal line 12.

FIG. 4 shows the configuration of the memory section 5 and address calculation section 6. In the figure, 40 is a memory data read register (
MDR, 几1), 41 is memory 1.42 is memory data write register 1 (MDWRI), 43 is memory address register 1 (MARL), 44 is memory data read register 2 (MD几FL2), 45 is memo+72.
46 is a memory data write register, 47 is a memory address register 2, 48, and 49 are MDf'Lf, respectively.
'L1 (40), a signal line that outputs the data of MD FL2 (41) to the data bus 16; 50, a selector that selects the output of the arithmetic logic unit (ALU) 53 and one of the data buses 16; 51 is a 2-vote register (
BEG), 52 is MDRR1 (40), MDRR,2 (
44) is a selector for selecting one of the outputs of the EG51.

The two memos 1J41 and 44 have the same function; for example, in the memory 41, when reading, MAR1 (43)
Read the data at the address specified in MDR,
Set to ELl (40). When writing, M
Write the data of DWRI (42) to the address specified by MAfLl (43).

MDWRI (42) can set data from the data bus 16, and MDRRI (40) can set data from the data bus 16, adder right input (12), adder present input (13),
The configuration allows output to the signal lines of the multiplier right input (14) and multiplier existing input (15).

In addition to being able to set the output of the ALU 53, MAR,1 (43) also has the function of counting up and down by (2).

RgGsi is two read addresses WKI.

It is a two-vote register with WK2, and writes are written to the WKI address in the second half of one machine cycle. The right input of ALU53 is data from REG51,
The left input is EG51. MDRRI (40).

MDRR, 2 (44) is used for calculation, and the result is MAR1 (43), MAR2 (47).
).

Can be set to REG51.

The operation of each of the units 3 to 6 in one machine cycle is defined by one word of the microprogram in the microprogram controller 7. Outputs from each unit of signal lines 12 to 16 are specified so that only one is selected.

FIG. 5 shows a specific example of the pipeline multiplication circuit 10 according to the present invention. In the figure, 101 and 102 are exponent part input control circuits, 103 and 104 are registers, 105 is an adder, 106 is a selector, 107 is an adder, and 108, 1
09 is a register, 110 is an adder, 111 is an 808 circuit, 112゜113.114 is a register, 115, 11
6 is a mantissa input control circuit, 117 and 118 are registers, 119 is a partial product multiplication circuit, 120 is a register, 121
is a selector, 122-digit adder, 123 is a shifter, 124
125 is a register, 125 is a selector, 126 is an output control circuit, 127 is a selector, 128 is a code signal line, a 129-digit exponent signal line, and a 130-digit mantissa signal line. The number of lowercase 0 characters added to each signal line is the number of signal lines (
number of bits).

Input control circuit 101, 102, 115° 116 in FIG.
register 103 depending on whether the data is single or double precision.
, 104, 117, and 118. The format of single-precision and double-precision data is shown in FIG. The data expressed at this time is (1) X2 Xl in single precision, and (1) X2 Xi, Fn in double precision. However, B
5 and BD are the bias portions of the exponent parts Es and ED, respectively.

FIG. 7 shows the configuration of the exponent part input control circuit 101. SS in the figure is "1" when the input is single-precision data, and is rOJ otherwise.

5s=rl'', the 1st to 8th bits of input data are output to the 4th to 11th bits of the output signal line via gates 1-03, and the 1st to 3rd bits of the output signal line are output to the gate G.
1, "o" is output. When SS-l"'oJ, the input data is output as is through gates G2 and G4. As a result, the register 103 has exponent data aligned to the right for both single and double precision. , is set.

Exponent input control circuit 102 also has the same configuration as 101,
The data of the exponent part is output and set in the register 104. EOR1x+ takes the EOR of the sign bits of two input data. As a result, the sign of the product of the two data is obtained, and this is set in the register 112.

The configuration of the mantissa manual ftjlJ control circuit 115 is shown in FIG. In the figure, 88. DU and DL indicate that the input data is "1" when the input data is the upper 32 bits of single precision, the upper 32 bits of double precision, and the lower 32 bits of double precision, and is "0" otherwise. SS - When "1", 0 of the output signal line
The 7th to 7th bits are rOJ through the gate Gll, the 8th bit is 1 through the gate G13, and the 9th to 31st bits are the input signal lines 9 through G20.
The 31st bit data is output. Here, the reason why the 8th bit is output as rlJ is because of the data format.
It is used to raise hidden bits. DU=
When rlJ, gate Gll.

G14. The 0 to io pits of the output signal line are set to "0" through G16, and the 11th bit is set to "1" through gate 018.
However, for the 12th to 31st pits, the data of the 12th to 31st pits of the input signal line are outputted via the gate G20, respectively.

When DL=rlJ, gate G12. G15. G17
．． G19. Input data is output as is to the output signal line via G20. The mantissa input control circuit 116 is also 115
The outputs of 115 and 116 are set in registers 117 and 118.

In the adder 105, the data in the registers 103 and 104 are added, and the result becomes the left input of the adder 107.

Here, Eel is the exponent part of the two single-precision data.

EI! 2, the exponent part is multiplied by 2Kill
-Blil EB -811,,,2E[Il+E
l! 2-2BII×2 = 2 (“s+”+!2 Bs)-111! It is necessary to add . To output in single precision, E s
Add I and 8g of E, then add B11
It is necessary to subtract. Similarly, when the input is double precision and the output is double precision, it is necessary to add the exponent parts and then subtract the bias amount Ba.

The selector 106 and adder 107 are circuits that perform this correction. Selector 106, when the input data is single precision and the output is also single precision, Bs, when both the input and output are double precision,
Select BD.

The adder 107 subtracts the right input data from the value of the left input data and outputs the result. The result is set in register 108. The contents of register 112 are transferred to register 113 and set.

FIG. 9 shows the configuration of partial product multiplier 119.

201 to 204 are multiplied by 16-bit input data to obtain 3
This is a multiplier that produces a 2-bit output. 201 is the multiplication of the upper 16 bits of the input data, 202 is the multiplication of the lower 16 bits of the left input, the upper 16 bits of the right input is multiplied by n, and 203 is the multiplication of the upper 16 bits of the left input and the lower 16 bits of the right input. , 204 input data are multiplied by the lower 16 bits, and the result is set in the register 120.

The operation of the adder 122 will be explained separately into single-precision multiplication and double-precision multiplication.

First, during single-precision multiplication, l'-oJ is selected by the selector 121, and the outputs of the register 120 are added together in the force 6 multiplier 122 as shown in FIG. 10, and the result is set in the register 124.

Next, when performing double-precision multiplication, the upper 32 bits of both the multiplicand and the multiplier are multiplied, and then the upper 32 bits of the multiplicand and the lower 32 bits of the multiplier are multiplied.
Multiply the bits, then multiply the lower 32 bits of the multiplicand by the upper 32 bits of the multiplier, and finally multiply the lower 32 bits of both the multiplicand and the multiplier.
This is done in the order of bit multiplication. The above four steps will be explained in detail using FIG. 11 in order. In the figure, 500(a) and 501(b) represent the upper 32 bits, lower 32 bits, and 502(C) of the mantissa part of the multiplicand, respectively.
.

503 (d) are the upper 32 bits of the mantissa of each multiplier,
This is the lower 32 bits.

First, in the first step, 500X502 (a×C)
The adder 122 adds the 64-bit data 504 and 505 "0" selected by the selector 121, and the resulting 75-bit data 506 is stored in the register 124.

In the second step, 6 of 500X503 (axd)
The 4-pit data 508 and the data 507 obtained by shifting the 75-bit data 506 stored in the register 124 by 32 bits to the left by the shifter 123 are transferred to the selector 12.
1 is selected, both are added by the adder 122, and the upper 75 bits 509 of the modification result are stored in the V raster 124.

In the third step, 6 of 501X502 (bxc)
The 4-pit data 510 and the 75-pit data 509 stored in the register 124 are transferred to the shifter 12 with a shift number O.
3 (that is, not shifted at all), is selected by selector 121, and both are added by adder 122, and the upper 75 bits 511 of the addition result are stored in register 124.

In the fourth and final step, 501X503 (bxd)
The 64-bit data 512 of
The 75-bit data 511 stored in the 24 is shifted by the shifter 123 with a shift number of 0 (that is, not shifted at all) and selected by the selector 121, and both are added by the adder 122 and the addition result is The upper 75 bits 514 are stored in register 124 register.

Note that the shifter 131 always outputs data with a shift number of 01, that is, without shifting at all, except in the fourth step of double precision multiplication.

As shown in FIG. 12, the multiplication results stored in the register 124 have two patterns for single-precision multiplication and double-precision multiplication. Pit 16.0 during single precision multiplication
~15.64-74 is O, bit 16 is 1, bit A17-63 is 0 or 1 pattern, pit width 0-16.64-74 is O, bit &17 is 1, pit A 18-63 is a pattern of 0 or 1.

This is because, as shown in FIG. 8, the input data of the mantissa part is processed and set.

For the same reason, when performing double-precision multiplication, the 2
There is a common pattern.

For each of two patterns, the selector 125 performs a function similar to a shift so that bit A23 is set to 1 for the first time in single precision and double precision, respectively, and the output is outputted at 130.

FIG. 13 shows the configuration of the output control circuit 126 of the sign part, exponent part, and mantissa part calculation circuit.

In the figure, 88. D is a signal indicating single-precision and double-precision arithmetic, respectively. OE is an output permission signal.

This circuit outputs a sign part and an exponent part.

The operation result is output with the mantissa in the correct floating point format.

According to this embodiment, even during double-precision multiplication, it is possible to start from the multiplication of 32-pit data including the MSB of the mantissa part, and the memory access data is supplied to the pipeline arithmetic unit without any empty space.1) Hypline This is effective in improving the overall throughput of calculations.

〔Effect of the invention〕

According to the present invention, double-precision floating point data can be supplied to the pipeline multiplier in the order of the upper 32 pits and the lower 32 bits, so compared to the conventional case where the data is supplied in the order of the lower 32 pits and the upper 32 bits, In double-precision multiplication, the speed can be increased by two machine cycles.

Furthermore, according to the present invention, even when the IEgE standard floating point format is adopted, the data in the exponent part is read out at the same time at the start of multiplication, so non-numbers are recognized quickly and there is no disturbance in pipeline operation. It disappears.

[Brief explanation of the drawing]

3 is a configuration diagram of the register file in FIG. 1, FIG. 4 is a configuration diagram of the memory and address arithmetic unit in FIG. 1, and FIG. 5 is a configuration diagram of the multiplication circuit according to the present invention. A configuration diagram of one embodiment, FIG. 6 is a diagram explaining the floating format, FIG. 7 is a configuration diagram of the exponent input control circuit in FIG. 5, and FIG. 8 is a configuration diagram of the mantissa input control circuit in FIG. 5. , FIG. 9 is a block diagram of the partial product multiplier in FIG. 5, FIG. 10 is a diagram explaining addition of partial products, FIG. 11 is a diagram explaining the procedure for double precision multiplication,
This figure is a diagram explaining the format of the multiplication result, and FIG. 13 is a configuration diagram of the output control circuit in FIG. 5. 10... Pipeline multiplier L119... Partial product multiplier, 122... Adder, 131... Shifter. ￥90 Judgment 10 pieces/Zg 1st/Figure rod IZth

Claims (1)

[Claims] 1. A partial product multiplier that multiplies a multiplicand divided into multiple blocks and data serving as a multiplier for each block, and performs multiplication by accumulating the multiplication results, and performs multiplication on a block-by-block basis. In a multiplication circuit having an adder which takes the multiplication result of the partial product multiplier as one input and takes the accumulated multiplication result as the other input, the multiplication result of the partial product multiplier is multiplied by the number of bits of the block length. 1. A multiplication circuit comprising a shifter having a right-shifting function, and an output of the shifter is applied to one input of the adder.