JPH07104777B2 - Floating point adder / subtractor - Google Patents

Description

TECHNICAL FIELD The present invention relates to an adder / subtractor in a data processing device,
In particular, the present invention relates to a floating point adder / subtractor suitable for rounding operation results.

[Prior Art] Conventionally, Japanese Patent Laid-Open No. 61-213927 is known as an example of a floating-point addition / subtraction device that performs rounding depending on the logical sum of all bits lower than the rounding bit.

In this example, the bit length of the mantissa part is set longer than the numerical expression type (eg, 67 bits) inside the device, and when rounding is performed, the logical sum of all bits lower than the rounding bit is calculated. When the standard format of task P754 is adopted, the bit length lower than the rounding bit is 41 bits for single precision, 11 bits for double precision, and 1 bit for extended precision.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional floating-point addition / subtraction device, in the digit alignment of mantissas in which the exponents have the same magnitude in double precision and extended precision of the IEEE standard format shown in FIG. There has been a problem that it takes a long time to perform an OR operation of all bits lost by right shift, and it takes a long time to right shift.

On the other hand, in single precision, there is a problem that it takes time to perform an OR operation of 41 bits lower than the rounding bit, and it takes a long time for the rounding process.

In order to solve the above-described problems of the prior art, the present invention enables high-speed rounding processing by predicting the logical sum of all bits lower than the rounding bit without directly depending on the bit width of the internal arithmetic unit. It is an object of the present invention to provide a floating point adder / subtractor.

[Means for Solving the Problem] In order to achieve the above-mentioned object, the floating-point addition / subtraction device of the present invention inputs the operands and the operands of the same numerical expression format consisting of a sign, an exponent part, and a mantissa part, A floating-point adder / subtractor that outputs an addition / subtraction result in the same numerical expression format as the operand and the operation number, and depends on the logical sum of all bits below the rounding bit for the intermediate mantissa operation result In a floating-point adder / subtractor that performs rounding, the logical sum of all bits lower than the rounding bits of the intermediate mantissa operation result is predicted, so that the mantissa of each of the operand and the operand is calculated. And a means for detecting a continuous bit length of "0" from the least significant bit is provided, and a continuous "0" corresponding to a number having a smaller exponent from the continuous bit lengths of the two "0" s. Select to select the bit length Alternatives,
There is provided a magnitude comparison means for comparing the consecutive bit lengths of "0" output by the selection means and the bit length lost when the mantissa corresponding to the smaller exponent is right-shifted to match the exponent size. It is characterized by that.

[Operation] According to the above-described configuration of the present invention, the continuous bit length of "0" from the least significant bit of the mantissa corresponding to the smaller exponent is set to the smaller exponent to match the exponent size. Introduces a spill bit with a value of "1" if it is less than the bit length lost when performing a right shift of the corresponding mantissa, and a value of "0" otherwise. By adding and calculating, the sticky bit which is the logical sum of all bits lower than the rounding bit can be predicted.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings.
The present invention is not limited to the following examples.

FIG. 1 shows the overall configuration of a floating point addition / subtraction device according to the present invention.

In FIG. 1, reference numeral 1 is a control circuit for controlling the entire apparatus,
Reference numeral 2 denotes a floating point register, which can store 32 pieces of floating point data of 1 bit 64 bits, and has two read ports and one write port. Three
Is an operand register, 4 is an arithmetic register, 5 is an absolute value subtractor, 6 and 7 are leading bit addition circuits, and 8 and 9
Is a zero-detection circuit for detecting consecutive bit lengths of "0" from the least significant bit, 10, 11, 12, 13, 14 are 2: 1 multiplexers, 15 are inverting circuits, 16 are 2: 1 multiplexers, 17 Is a preshifter, 18 is a magnitude comparison circuit, 19 is an absolute value adder, 20 is an inverting circuit, 21 is a 2: 1 multiplexer, 22 is
Leading zero detection circuit that detects consecutive bit length of leading “0” from MSB, 23 is adder / subtractor, 24 is post shifter, 25
Is a rounding data generation circuit, 26 is a rounding adder, 27 is a constant adder, and 28 is a 2: 1 multiplexer.

The numerical representation format of the floating point data handled by this floating point adder / subtractor is the double precision format of IEEE Task p754 as shown in FIG.

First, the operand and the operand are read from the floating point register 2 and set in the operand register 3 and the operand register 4, respectively. In the control circuit 1, it is determined whether the instruction is an addition or a subtraction, the operand and the sign of the operation number, and whether the addition / subtraction device as a whole substantially performs addition or subtraction. The absolute value subtracter 5 inputs the operands output from the operand register 3 and the operand register 4 and the exponent part of the operands to find the difference, and outputs the absolute value and outputs the absolute value. Outputs the comparison result of the exponent of the operand and the exponent of the operand.

On the other hand, in the mantissa part of the operand and the operand output from the operand register 3 and the operand register 4, the leading bit is added by the leading bit adding circuits 6 and 7, and the trailing zero detection circuit 8 is added. 9 detects the bit length in which "0" continues from the least significant bit of the mantissa of the operand and the operand. In the multiplexers 10, 11, and 12, when the exponent magnitude comparison result output from the absolute value subtractor 5 is larger or equal to the operand, the mantissa to which the sign of the operand, the exponent, and the leading bit are added, In other cases, the sign, exponent, and mantissa to which the leading bit is added are selected and output. In the multiplexers 13 and 14, when the exponent magnitude comparison result output from the absolute value subtracter 5 is larger or equal to the operand, the mantissa to which the leading bit of the operand is added, the trailing zero bit length of the operand, In other cases, the mantissa to which the leading bit of the operand is added and the trailing zero bit length of the operand are selected and output. The inverting circuit 15 inputs the output of the multiplexer 12 and inverts and outputs each bit. The multiplexer 16 adds three bits of “0” to the lower order of the output of the multiplexer 12 in the case of actual addition. In the actual subtraction, the output of the inverting circuit 15 to which 3 bits of "1" are further added is selected. The preshifter 17 shifts the mantissa including the leading bit corresponding to the smaller exponent output from the multiplexer 13 to the right by the number of absolute values of the exponent difference sent from the absolute value subtractor 5. In the pre-shifter 17, the bit length of the mantissa part is extended to the lower two bits and right shift is performed. When the shift number is larger than 2, the bits overflowing from the shifter are lost. The magnitude comparison circuit 18 compares the absolute value of the difference between the exponents sent from the absolute value subtracter 5 with the value obtained by adding “2” to the zero bit length of the trace corresponding to the one with the smaller exponent output from the multiplexer 14. , If the absolute value of the difference between the exponents is larger, the spill bit is output as "1", otherwise the spill bit is output as "0".

Next, in the absolute value adder 19, the output of the multiplexer 16 is used as the first input, and the output of the preshifter 17 to which the spill bit output from the magnitude comparison circuit 18 is added is used as the second input. However, the control circuit 1 sends "0" as the initial carry at the time of substantial addition and "1" at the time of actual subtraction to execute the two's complement addition, then the addition result is converted to an absolute value, and the third value is added. The intermediate calculation result shown in the figure is output. The inverting circuit 20 inverts the output of the multiplexer 10,
Before the actual subtraction and the absolute value are taken, the multiplexer 21 uses the information indicating the actual subtraction sent from the control circuit 1 and the sign of the addition result before the absolute value sent from the absolute value adder 19 (not shown). When the sign of is positive, the output of the inverting circuit 20 is selected, and in other cases, the output of the multiplexer 10 is selected and output. In leading zero detection circuit 22, a third bit 56 shown in FIG. (Indicating 2 ¹ ... position of bits, the same below), bit 55 value of (2 ...) is "01" and so as an absolute value The shift number for shifting the output of the adder 19 is obtained. At this time, 1 for right shift and 1 for left shift
There are 54 to 54 shifts, and sticky bits are not subject to shift. The adder / subtractor 23 is the multiplexer 11
When the right shift is performed, the shift number is added to the exponent output by, the shift number is subtracted when the left shift is performed, and zero is added when the shift is not performed, and the exponent is output. In the post shifter 24, the absolute value adder corresponding to the output of the leading zero detection circuit 22
Shift 19 outputs. At this time, in the case of right 1 bit shift, the logical sum of bit 1 (2 ^-54 ) and bit 0 (sticky bit) is changed to bit 0, and in the case of left shift, bit 0 does not change anything. Zeros are added to the bits that have become vacant due to the left shift.

Next, in the rounding data generation circuit 25, bit 3 is selected from the code output from the multiplexer 21 and the output from the post shifter 24.
Input the LSB of (2 ^-52 ), the guard bit of bit 2 ( ^-53 ), the round bit of bit 1 (2 ^-54 ), the sticky bit of bit 0, and the rounding mode bit from the control circuit 1 ( (Not shown), FIG. 4 (a) (b)
Carries to the rounding adder 26 are generated and output so that the rounding processing shown in (c) and (d) is performed. The constant adder 27 adds the constant “1” to the exponent output from the adder / subtractor 23 and outputs the result. In the rounding adder 26 bits 56 (2 ¹⁾ multiplexer 28 when there is a carry to the output of the constant adder 27,
In other cases, the output of the adder / subtractor 23 is selected as the exponent part of the final calculation result. The mantissa part of the final operation result is rounding adder 26 excluding leading bits.
It outputs 52 bits from bit 54 to bit 3 of. bit
Even if there is a carry to 56 (2 ¹ ), the reason why there is no problem in the above selection is that the corresponding carry after bit 55 to bit 3 53
This is because the bits are all zero, and selecting bit 4 from bit 55 will result in the same selection as above.

Finally, the final operation result obtained as described above is written in the floating point register 2, and the floating point addition or floating point subtraction is completed.

In this embodiment, only the double-precision numeric format of the IEEE standard floating-point data is handled. However, in the case of other numeric formats as well, all bits lower than the rounding bit for the intermediate mantissa operation result The present invention can be applied to predict the logical sum of

[Effect of the Invention] According to the present invention, a floating-point addition / subtraction device that performs rounding processing depending on the logical sum of all bits lower than the rounding bit, Also, instead of taking the logical sum of all the lower bits, the logical sum can be predicted from the operand and the mantissa part of the arithmetic number.
An excellent effect that the rounding process can be executed at high speed can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a floating point addition / subtraction device according to the present invention, FIG. 2 is a diagram showing an IEEE standard floating point data numerical representation format, and FIG. 3 is a floating point addition / subtraction of one embodiment of the present invention. FIGS. 4A, 4B, 4C, and 4D are diagrams showing a conventional rounding process, which are diagrams showing intermediate mantissa part calculation results by the apparatus. 1 ... Control circuit, 2 ... Floating point register, 3 ... Operand number register, 4 ... Operand number register, 5 ... Absolute value subtractor, 6,7 ... Leading bit addition circuit, 8,9 ... …
Depressing zero detection circuit, 10,11,12,13,14,16,21,28 …… Multiplexer, 15,20 …… Inversion circuit, 17 …… Preshifter, 1
8 …… size comparison circuit, 19 …… absolute value adder, 22 …… leading zero detection circuit, 23 …… adder / subtractor, 24 …… post shifter,
25 …… Synchronous zero register, 26 …… Rounding adder, 27 …… Constant adder.

Claims (1)

[Claims] 1. Floating-point addition / subtraction for inputting an operand and an operand in the same numerical expression format consisting of a sign, an exponent, and a mantissa, and outputting an addition / subtraction result in the same numerical expression as the operand and the operand. An intermediate mantissa operation in a floating-point addition / subtraction device that is a device and performs rounding on the intermediate mantissa operation result depending on the logical sum of all bits lower than the rounding bits. In order to predict the logical sum of all bits lower than the rounding bit of the result, detect the consecutive bit length of "0" from the least significant bit for each mantissa part of the operand and the operand. Means for selecting, from the two consecutive bit lengths of "0", a selecting means for selecting a consecutive bit length of "0" corresponding to a number having a small exponent, and "0" output by the selecting means. Of consecutive bits and the large exponent Floating point addition and subtraction apparatus characterized in that a magnitude comparison means with the bit length to be lost when shifting right mantissa corresponding to the smaller index to match the of.