JP3257278B2 - Normalizer using redundant shift number prediction and shift error correction - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating-point arithmetic unit for performing addition and multiply-accumulate operations on floating-point numbers requiring normalization processing.

[0002]

2. Description of the Related Art As a method of expressing a floating point number on a computer, a standard format defined by IEEE-754 is generally used. A floating-point number represented by data including a sign s, an exponent part e, and a decimal part f takes a numerical value represented by the following equation.

(-1) {s × 2} (e−b) × (1.f) (1) where b is called an exponential bias, and is a value that is about half of the maximum value of the exponent part e. is there. An integer 1 is added to the decimal part f, and the integer part and the decimal part are collectively called a mantissa part. The numerical value represented in this way is called a normalized number.

Next, the floating point arithmetic processing will be described. For simplicity, consider the subtraction of two floating-point numbers represented by equations (2) and (3) with 1 bit for the sign, 3 bits for the exponent part, and 4 bits for the decimal part.

(-1) {0 × 2} (4-b) × (1.0011) (2) (-1) {0 × 2} (2-b) × (1.0001) (3) First, before performing the subtraction, match the exponents of the two numerical values to the larger one. At this time, the mantissa having the smaller exponent is shifted downward by the difference of the exponent. This processing is called digit alignment, and converts equation (3) into equation (4).

(-1) {0 × 2} (4-b) × (0.010001) (4) Next, the mantissa of equation (4) is subtracted from the mantissa of equation (2). The result is shown in equation (5).

(-1) {0 × 2} (4-b) × (0.111011) (5) In the mantissa part of the equation (5), the integer part is 0 and is not a normalized number. In order to make this a normalized number, the most significant 1 of the mantissa is first found (the first digit to be 1 when viewed from the most significant digit), and the entire mantissa is shifted such that this digit comes to the integer part. Next, the number obtained by shifting the mantissa part from the exponent part is subtracted.
This process is called normalization, and converts equation (5) into equation (6).

(-1) {0 × 2} (3-b) × (1.11011) (6) Since the decimal part of the equation (6) has 5 digits, it is converted to the number of digits of the format (4 digits). ) Is performed. This is called a rounding process. Equation (7) shows an example of rounding equation (6).

(-1) {0 × 2} (3-b) × (1.110) (7) The above is an example of the floating-point arithmetic processing. As a conventional example of such a method of calculating a floating-point number, Japanese Patent Laid-Open No.
There is a method described in -232723. An arithmetic device using this method will be described with reference to FIG.

The digit matching circuit 15 performs addition and subtraction on 2
Input two floating point operands 110 and 111,
Both exponents are matched to the larger value, and the smaller mantissa of the exponent is shifted downward by the difference of the exponents.
The addition / subtraction circuit 10 includes a combination of an operation instruction 112 and signs of input operands 110 and 111, an exponent part,
The mantissa part 11 after digit matching corresponding to the magnitude relation of the mantissa part, etc.
Addition and subtraction of 3,114 are performed. The shift number calculation circuit 90
The number of digits from the first digit to the integer part of the addition / subtraction result 103 is calculated as the shift number 180. Normalized shift circuit 1
2 shifts the addition / subtraction result 103 using the shift number 180. The rounding circuit 16 performs an operation for reducing the normalized shift result 105 to the number of digits of the format. The exponent part correction circuit 17 outputs the exponent part 1 output from the digit matching circuit 15.
A value 116 obtained by subtracting the shift number 180 from 15 and a value 117 obtained by adding 1 to the value 116 are output. The exponent part selecting circuit 18 corrects the exponent parts 116 and 117 according to the rounding result 115.
Select one of Through the above processing, the calculation result 119 of the floating-point number is generated.

[0011]

However, in the conventional arithmetic unit, since the normalized shift number is calculated using the result of addition and subtraction, the normalization process takes a long time, which hinders an increase in speed.

An object of the present invention is to provide an arithmetic method capable of performing normalization processing at higher speed. Another object of the present invention is to provide a floating-point arithmetic device that can perform addition and subtraction of floating-point numbers and product-sum operation at higher speed by speeding up normalization processing.

[0013]

In order to achieve the above object, a floating point arithmetic unit according to the present invention uses a shift number redundant prediction means for predicting a normalized shift number within an n-bit error using input data for addition and subtraction. A shift error detecting means for detecting a difference between the predicted shift number and the accurate shift number, and an n-bit shifter for shifting the result of the normalized shift using the predicted shift number by the number of shift errors.

Here, the operation algorithm used for the shift number redundancy prediction means will be described. This algorithm is
The carry propagation over a long bit and the number of logic stages required for the addition / subtraction process are not required, and the signal propagation between at most two bits and the number of logic stages are two stages. Can be sought within. First, the data after the complement processing is A and B.

A = A [0] A [1]... A [n] (8) B = B [0] B [1]... B [n] (9) 10) and (11) are performed.

X = A ＾ B (10) P = A || B (11) where “＾” is an exclusive OR operator, and “||”
Is a logical OR operator. Next, X and P are expressed by equation (12).
Is performed.

Z = X ＾ (P << 1) (12) where “<<” is a shift operator and “P << 1”
Means that P is shifted one bit to the left. However, digits beyond the highest digit before the shift are ignored. Equation (1
Z in 2) represents “0” that continues from the most significant digit of the addition result. Actually, description will be made using specific numerical values.

A = 010110100 (13) B = 10111101 (14) When these are substituted into Expressions (10) and (11), X = 11100100 (15) P = 11111101 (16) By substituting these into equation (12), the following result is obtained: Z = 00011110 (17). This indicates that, as a result of adding A and B, "0" continues in the upper three digits, and "1" becomes the first in the fourth digit. Actually, the result of adding A and B is as follows: S = 00001010 (18), and the most significant digit of the expression (17) and the expression (18) match. Another example is as follows: A = 01000011 (19) B = 101111101 ... (20) X = 11101100 ... (21) P = 11111101 ... (22) Z = 000110110 ... (23) S = 000011010 ... (24) Thus, the most significant digit does not match in Expression (23) and Expression (24). As described above, the most significant 1 in the calculation result of Expression (12)
Is either equal to that of the addition result or one digit higher. This is because equation (12) can accurately calculate a value other than the last “0” among the consecutive “0” s from the most significant digit of the addition result. Proof about this.

The i-th digit of the result of adding the expressions (8) and (9) is S
When [i] and the (i + 1) th digit are S [i + 1], S [i] = X [i] ＾ C [i + 1] (25) = X [i] ＾ (G [i + 1] | (P [i + 1] & C [i + 2])) (26) S [i + 1] = X [i + 1] ＾ C [i + 2] (27) where X [i + 1], G [i + 1], P [i + 1]
Are exclusive OR, AND, and OR of the two inputs at the (i + 1) th digit, respectively, and C [i + 1] is i
The carry to the digit. The symbols “記号”, “&”,
“|” Means a bit operator of exclusive OR, logical product, and logical OR, respectively. Here, S [i] and S [i +
1] is “0”, and the equation (26) is modified. First, from Expression (27), X [i + 1]］ C [i + 2] = 0 (28) X [i + 1] = C [i + 2] (29) is derived. Next, the expression (29) is substituted into the expression (26), and X [i] ＾ (G [i + 1] | (P [i + 1] & X [i + 1])) = 0 (30) is derived. Since G [i + 1] | (P [i + 1] & X [i + 1]) = P [i + 1] (31), Expression (30) is further transformed into Expression (32).

X [i] ＾ P [i + 1] = 0 (32) That is, when both S [i] and S [i + 1] are “0”, equation (32) is established. When this is extended, when all the digits from the most significant digit to the (i + 1) th digit of the addition result are “0”, Expression (32) is established for the i-th digit from the most significant digit. This is equivalent to the fact that all the i-th digits from the most significant digit of Expression (12) are “0”. From the above, using the result of equation (12), 1
It has been proved that the most significant 1 of the addition result can be predicted within an order of magnitude error.

[0021]

As described above, by predicting the normalized shift number within an n-bit error using the input data for addition and subtraction, the calculation of the normalized shift number and the addition and subtraction can be performed in parallel. Further, a correct normalization result can be generated by the shift error detection and the normalization shift correction.

[0022]

FIG. 2 shows an example of a computer system using the present invention. A plurality of computers including a processor 21, a memory 22, and a hard disk 23 are connected via a general network 20. In such a computer system, the present invention is applied to a processor 21 that performs a numerical calculation process.

FIG. 3 shows an example of the processor 21. A data cache 30 and an instruction cache 33 are built in so that data and instructions can be accessed at high speed. The memory address conversion from the virtual address to the physical address is performed using the data TLB31 and the instruction TLB32. This control is performed by the memory control unit 34. The integer operation is performed by the general-purpose registers 35, the ALU 36, and the ALU 37. The calculation of the instruction address is performed using the address adder 38. The floating-point operation includes a floating-point register 40, a floating-point adder 41, a floating-point multiplier 42, and a floating-point divider 43.
Do with. These controls are performed by the instruction control unit 39.
2. Description of the Related Art Very high floating-point arithmetic performance is required in computer applications such as scientific computing and computer graphics. In particular, floating-point addition is frequently used among floating-point operation instructions, and a floating-point adder capable of high-speed operation is important. The present invention relates to such a floating point adder 4.
Applies to 1.

FIG. 4 shows an embodiment of the floating point adder 41. In FIG. 4, 10 is an addition / subtraction circuit, 11 is a shift number redundancy prediction circuit, 12 is a normalized shift circuit, 13 is a shift error detection circuit, 14 is a normalized shift correction circuit, 15 is a digit matching circuit, 16 is a rounding circuit, Reference numeral 17 denotes an exponent part correction circuit, and reference numeral 18 denotes an exponent part selection circuit. The arithmetic unit according to the present embodiment adds or subtracts two input operands (110, 111) according to the operation instruction (112), and outputs a result (119) obtained by performing normalization and rounding processing.

Hereinafter, the IEEE-754 double-precision format will be described as an example. However, the effects of the present invention are not limited to this, and the present invention is not limited to a single-precision format, a quad-precision format, and other than the IEEE format. Is also widely available.

Hereinafter, this embodiment will be described in detail with reference to the drawings.

First, the digit matching circuit 15 will be described. FIG. 5 shows the input operand (11
0, 111) and the mantissa parts fa (113), fb (114) of the digit alignment result. Table 1 shows the function of the digit matching circuit 15. Exponent part ec after digit alignment
(115) is the two input operands (110, 111)
Take the larger value of the exponent parts e1 and e2. The mantissa part fa (113) after digit alignment is a value obtained by adding an integer value 1 to the larger decimal part of the exponent part. The other mantissa part fb (114) after the digit alignment is a value obtained by adding an integer value 1 to the smaller fraction part of the exponent part and shifting it downward by the difference of the exponent part. Here, the signal b55 of the least significant digit of fb (114) is the OR of all the signals dropped from the 55th digit by the shift. Speaking of the addition or subtraction targeted by the present embodiment, there is no problem in calculation accuracy even if the number of digits for digit alignment is limited to 55 decimal places.

[0028]

[Table 1]

According to the operation instruction (112) and the values of the signs s1 and s2 of the input operands (110 and 111), the processing of the mantissa after digit alignment is substantially added (fa + f).
b), substantial subtraction A (fa−fb), substantial subtraction B (fb−f
a). In order for this processing to be performed by the addition / subtraction circuit 10, a complement control signal 116 is generated by the digit alignment circuit. Table 2 shows an example of the complement control signal 116, which is composed of three signals 117, 118 and 119. 117
Is a signal that becomes 1 in the case of the substantial subtraction B, and is used to take the complement of the mantissa part fa after digit alignment. Reference numeral 118 denotes a signal which becomes 1 in the case of the substantial subtraction A.
Used to take the complement of b. 119 is a signal which becomes 1 in the case of the substantial subtraction A or the substantial subtraction B.
It is used as the complement of 1 when performing subtraction with 0.

[0030]

[Table 2]

Next, the addition / subtraction circuit 10 will be described.
FIG. 6 is a block diagram of an example of the add / subtract circuit 10, which is a carry look-ahead adder often used in an LSI. Complement circuit 5
Numerals 0 and 51 are circuits that take the complement of the mantissa part fa (113) or the mantissa part fb (114) in the case of substantial subtraction. Complement control is performed using signals 117 and 118, respectively.
The outputs 120 and 121 of the complement circuits 50 and 51 are first divided into several fields each having several bits, and the addition is performed for each of these fields. 52, an adder circuit assuming that there is no carry from the lower order; 53, an adder circuit assuming that there is a carry from the lower order; 54, an adder using the complement control signal 119 as a carry to the least significant digit Circuit. Here, it is assumed that the left side in the figure is the upper digit side. The adders 52, 53 and 54 calculate the sum 122 and carry 123 of each field. The carry 123 is input to the carry propagation circuit 55, and the correct carry 124 for each field is calculated. Reference numeral 56 denotes an addition result selection circuit that selects the correct one of the sum 122 of the addition circuit 52 or the addition circuit 53 for each field using the carry 124. By the above processing, the addition / subtraction result S1 S0.s
1 ... s55 is obtained.

Next, the shift number redundancy prediction circuit 11 will be described. FIG. 7 is an example of the shift number redundancy prediction circuit 11. The mantissa part fa (11) output from the digit matching circuit 15
3), fb (114) and complement control signals 117, 11
Using 8, the number of digits from the first digit when viewed from the most significant digit of the output 103 of the addition / subtraction circuit 10 to the integer part is predicted within a 1-bit error.

In FIG. 7, the complement circuits 60 and 61 provide a mantissa part fa (113) or a mantissa part fb
This is a circuit that takes the complement of (114). Complement control is performed using signals 117 and 118, respectively. The continuous 0 detection circuit 62 outputs the output signals 130, 13 of the complement circuits 60, 61.
When 1 is added, this circuit obtains 0s consecutive from the most significant digit to the lower direction of the result. FIG. 8 shows a detailed circuit diagram of the detection circuit 62 for continuous 0. This circuit converts the output signals 130 and 131 of the complement circuits 60 and 61 for each bit,
After taking OR (logical sum) and XOR (exclusive OR), XOR of the XOR signal and the OR signal one bit lower is taken. The resulting 55-bit signal z0 z1 z
2... Z54 become the continuous 0 detection result 132. In this signal, z0 corresponds to the integer part immediately to the left of the decimal point, and z1.
54 corresponds to the first to 54th digits of the decimal part. For example,
If z0... z5 are all 0 and z6 is 1, the most significant 1 of the addition result is considered to be the sixth digit of the decimal part, and the shift number is set to 6. However, this value includes a one-bit error. In this example, the most significant one of the addition result is the sixth decimal part.
It is not the digit but the fifth digit, and the shift number may be predicted to be increased by one, as in the case where it is correct to set the shift number to 5. This means that the correct carry must be input to the last digit of consecutive 0s for accurate consecutive 0 detection, but the circuit of FIG. 8 uses the signal of the immediately lower digit instead of the correct carry. This is because OR is used. Although there is a one-bit error in this way, the circuit shown in FIG. 8 can detect consecutive zeros of the addition result with only two XOR circuits.

Returning to FIG. 7, the description of the shift number redundancy prediction circuit 11 will be continued. In FIG. 7, reference numeral 63 denotes a priority determination circuit, 64 denotes a byte shift number calculation circuit, and 65 denotes a bit shift number calculation circuit. As the normalization shift circuit 12 in this embodiment, an example of a two-stage shifter in which the addition / subtraction result 103 is first shifted in units of bytes and then shifted in units of bits as described later will be described. In such a shifter, the number of shifts is represented by the number of bytes and the number of bits,
It is necessary to input to the shifter of byte unit and the shifter of bit unit respectively. The byte shift number calculation circuit 64 generates a signal 147 indicating the shift number in byte units.
The bit shift number calculation circuit 65 generates a signal 148 indicating the shift number in bit units. Continuous 0 detection result 13
2 is input to seven priority determination circuits 63 by eight bits from the most significant digit. FIG. 9 shows an example of the highest priority determination circuit 63. The remaining priority determination circuits have the same configuration. The signals z0... Z7 of the upper 8 bits of the continuous 0 detection result 132 are input and the block OR signal 13
3 and an intra-block priority signal 139 are generated. The block OR signal 133 is an OR of an 8-bit input signal, and when this is 1, it means that 1 exists in the input signal. The in-block priority signal 139 is a signal in which only the one digit closest to the highest of the 8-bit input signal is set to 1 and all others are set to 0. However, when the upper 7 digits of the input signal are all 0, this digit may be regarded as 1 regardless of the value of the 8th digit of the input signal as shown in FIG.
This is because when the input 8 bits are all 0, the intra-block priority signal 139 is not used for subsequent calculations.

FIG. 10 shows an example of the byte shift number calculation circuit 64. The block OR signals (133 to 138) output from the upper six of the priority order determination circuits 63 are input to the byte shift number calculation circuit 64. This circuit sets only 1 signal closest to the top to 1 and sets all other signals to 0.
It works as follows. When the signals 133 to 138 are all 0, it is considered that the block OR of the lowest priority determination circuit 64 is 1. 7 generated in this way
The bit signals y0 y1... Y6 become signals 147 indicating the number of byte shifts.

Returning to FIG. 7, the bit shift number calculation circuit 65 will be described. The in-block priority signals 139 to 146 output from the seven priority determination circuits 63 are selected by the byte shift number 147, and the bit shift number is 148.

The byte shift number 147 and the bit shift number 148 obtained as described above become the shift number redundancy prediction result 104.

Next, the normalization shift circuit 12 will be described. FIG. 11 is a block diagram of an example of the normalization shift circuit 12, which performs a shift in two stages of a shift in bytes and a shift in bits. Reference numeral 70 denotes a circuit for selecting one of the seven inputs, and 57 circuits are used to constitute a 57-bit byte shifter. Each of the selection circuits 70 inputs seven signals lower than the output signal 103 of the addition / subtraction circuit 10 by an integer multiple of 8, starting with the signal corresponding to that bit. If there is no signal used for input, enter 0.
Selection of an input signal is performed using the byte shift number 147 output from the shift number redundancy prediction circuit 11 to generate a 57-bit signal Y1 Y0.y1 y2... Y55 (150). 71
Is a circuit for selecting one from eight inputs, and 57 circuits are used to constitute a 57-bit bit shifter. Each of the selection circuits 71 outputs the output signal 150 of the byte shifter.
Eight consecutive signals are input starting with the signal corresponding to the bit. If there is no signal used for input, enter 0. The selection of the input signal is performed using the bit shift number 148 output from the shift number redundancy prediction circuit 11 to generate a 57-bit normalized shift result N1 N0.n1 n2... N55 (105).

Next, the shift error detection circuit 13 and the normalized shift correction circuit 14 will be described with reference to FIG. The output signal 105 of the normalization shift circuit 12 is input, and the signal 10 is output by the result signal 106 of the shift error detection circuit 13.
5 is shifted as it is or one bit lower, and is output as a normalized shift correction result 107. 72 is 2
This circuit selects one of the inputs, and 56 of them are used to form a 56-bit 1-bit shifter. Each of the selection circuits 72 receives two of the normalized shift result signal 105, a signal corresponding to the bit and a signal one bit higher than the signal. The selection of the input signal is based on the normalized shift result signal 10.
This is performed using N1 which is the signal of the most significant digit of 5. That is, the 1-bit signal N1 itself is equal to the shift error detection result signal 106. When N1 is 0, the normalization shift is correctly performed, and no correction of the normalization shift is required. If N1 is 1, the normalized shift is incorrectly 1
Correction of the normalized shift is necessary because the bit shift is performed extra. In this way, correct normalized shift results U0.u1 u2... U55 (107) are obtained.

Next, the rounding circuit 16 will be described. FIG. 13 is a block diagram illustrating an example of the rounding circuit 16. 7
Reference numeral 3 denotes an increment circuit for generating a value 151 obtained by adding 1 to U0.u1 u2... U52 of the upper 53 digits of the normalized shift correction result 107. Numeral 74 denotes a rounding judging circuit which generates a carry signal 152 by rounding using lower-order signals u52 to 55 of the signal 107. 75
Receives the normalized shift correction result 107 and the increment result 151, selects the signal 107 if there is no carry signal 152 due to rounding, and if so, selects the signal 151 and rounds the result R1R0.r1... R52 (115). Is a rounding selection circuit. To find the two-digit integer part of the rounding result is
This is because if the normalized shift correction result 107 is all 1, a carry may occur due to rounding, and the uppermost digit may be shifted from the first digit of the integer part to the second digit. In this case, since the decimal part of the rounding result 115 is all 0, there is no need to shift the most significant 1 to the position immediately to the left of the decimal point.

Next, the exponent part correction circuit 17 will be described. FIG. 14 is a block diagram illustrating an example of the exponent part correction circuit 17. In FIG. 14, reference numeral 76 denotes a signal 14 indicating the byte shift number in the shift number redundancy prediction result 104.
7 is input, and this is a circuit for encoding this into a 3-bit signal 160. Reference numeral 77 denotes a circuit for inputting a signal 148 indicating the bit shift number in the shift number redundancy prediction result 104 and encoding the signal 148 into a 3-bit signal 161. Signal 16
When the signal 161 is adjusted below 0, a value 162 in which the shift number redundant prediction signal 104 is a binary number is generated. 78
Is the exponent 11 after digit matching output from the digit matching circuit 15.
This circuit outputs a value 163 obtained by subtracting the binary value 162 of the shift number redundancy prediction signal from 5 and a value 164 obtained by adding 1 to the value. Finally, the exponent part selection circuit 18 will be described. This circuit selects the output signal 164 of the exponent part correction circuit when the shift error detection signal 106 is present or the signal R1 of the rounding result 115 is 1, and otherwise selects the signal 163 and outputs the exponent part 118 of the result. Exponent part selection circuit. Signal 1 generated by the process described above
18 and the signal 115, the floating-point adder result 1
19 is assumed.

Tables 3 and 4 show specific examples of the shift number redundancy prediction in the embodiment of FIG. Both tables show main signals until the result 105 of the normalized shift circuit 12 is generated when the mantissa part 113 output from the digit matching circuit 15 is subtracted from 114. Table 3 shows an example in which the shift number redundancy prediction is correct.
The most significant 1 of 3 is at the first digit of the decimal point, and the value indicated by the shift number redundant prediction signal 147, 148 is 1 (0 byte, 1 bit). Therefore, the normalized shift result 105 is a normalized number. On the other hand, Table 4 shows an example in which the shift number redundancy prediction is erroneous, and the most significant 1 of the result signal 103 of the addition / subtraction circuit 10 is in the first digit of the integer part,
The value indicated by 7,148 is 1 (0 byte, 1 bit). Therefore, the normalized shift result 105 does not become a normalized number.

[0043]

[Table 3]

[0044]

[Table 4]

FIG. 15 is a block diagram showing a floating-point multiply-accumulate unit according to another embodiment of the present invention. This device assigns three input operands 170, 171, and 172 to operands 170 and 171 in accordance with operation instruction 173.
An operand 172 is added or subtracted from the product of 71, and normalization and rounding are performed to generate a result 119. 4 in that the digit matching circuit 15 is replaced with a product-sum operation circuit 80. The two mantissa parts 174 and 175 output from the product-sum operation circuit 80 are added or subtracted by the addition / subtraction circuit 10, and the normalized shift number is predicted by the 174 redundant shift number prediction circuit 11.

[0046]

The effects of the present invention will be described with reference to FIGS.

FIG. 17 shows a comparison of the critical path, which is a factor for determining the operation time, between the embodiment apparatus of FIG. 4 and the conventional apparatus of FIG. FIG. 1A shows a critical path of the conventional device. In FIG. 16, the output signal 113 of the digit matching circuit 15 is the start point of the path, and the output signal 105 of the normalization shift circuit 12 is the end point of the path.
FIG. 17B shows a critical path of the set value of the embodiment in FIG. In FIG. 4, the output signal 1 of the digit matching circuit 15
13 is the start point of the path, and the output signal 107 of the normalized shift correction circuit 14 is the end point of the path. In FIG. 17A, addition / subtraction, calculation of the number of shifts, and normalized shift are performed sequentially, whereas in FIG. 17B, addition / subtraction and calculation of the number of shifts are performed in parallel, and the number of logic stages is greatly reduced. are doing. After the normalized shift, new processing of shift error detection and normalized shift correction is required, but the speed of the entire critical path is increased.

FIG. 18 is a diagram comparing the operation time of the embodiment of FIG. 4 and the conventional device of FIG. The horizontal axis represents the operation time. As can be seen from FIG. 14B, the shift number can be calculated simultaneously with addition and subtraction.
The time required for normalization is less than half that of the conventional device. The comparison between the addition and subtraction and the normalization processing is 30
% Or more, 15% when compared in the whole floating point addition processing
The above speeding-up effect is obtained.

Further, in implementing the present invention, a logic circuit required for a continuous zero detection in the shift number redundancy prediction circuit and a normalization shift correction circuit is required as new hardware as compared with the conventional device. The number of gates required for these is about 1 to 2% of the entire floating point adder, and an increase in the number of gates can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a normalization device that best illustrates the features of the present invention.

FIG. 2 is an example of a computer system using the present invention.

FIG. 3 is a block diagram of a processor 21 in FIG. 2, which is an example of a processor to which the present invention is applied;

FIG. 4 is a block diagram of a floating-point adder according to an embodiment of the present invention.

FIG. 5 is an example of a method of expressing a floating-point number.

FIG. 6 is a detailed block diagram of the addition / subtraction circuit 10 of FIG. 4;

FIG. 7 is a detailed block diagram of a shift number redundancy prediction circuit in FIG. 4;

8 is a detailed logic diagram of the continuous 0 detection circuit 62 of FIG.

FIG. 9 is a detailed logic diagram of the priority determination circuit 63 of FIG. 7;

FIG. 10 is a detailed logic diagram of the byte shift number calculation circuit 64 of FIG. 7;

11 is a block diagram of the normalization shift circuit 12 of FIG.

FIG. 12 is a block diagram of the normalized shift correction circuit 14 of FIG.

FIG. 13 is a block diagram of the rounding circuit 16 of FIG. 4;

14 is a block diagram of the exponent part correction circuit 17 of FIG.

FIG. 15 is a block diagram of a floating-point multiply-accumulate unit as one embodiment of the present invention.

FIG. 16 is a block diagram of a conventional floating point adder.

FIG. 17 is a diagram comparing the critical path of the floating-point adder between the conventional apparatus and the embodiment apparatus of the present invention.

FIG. 18 is a diagram comparing the operation time of the floating-point adder between the conventional device and the device according to the embodiment of the present invention.

[Explanation of symbols]

10: Addition / subtraction circuit, 11: Shift number redundancy prediction circuit, 12
... Normal shift circuit, 13 ... Shift error detection circuit, 14
... Normalized shift correction circuit, 15 ... digit alignment circuit, 16 ...
Rounding circuit, 17: exponent correction circuit accompanying the normalized shift,
18. Exponent part selection circuit.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Hotta 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Hideo Sawamoto 1- 1 Horiyamashita, Hadano City, Kanagawa Prefecture, Ltd. (72) Inventor Takahiro Nishiyama 1st Horiyamashita, Hadano-shi, Kanagawa Hitachi Computer, Inc. General-purpose Computer Division (56) References JP-A-6-75752 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 7/50 G06F 5/01 G06F 7/00 G06F 17/10

Claims (3)

(57) [Claims] At least one input is a normalized binary expression of two positive binary operands whose most significant digit is 1, and by specifying an addition or subtraction operation,
Addition / subtraction means for adding or subtracting the two operands; normalization shift means for shifting the entire addition / subtraction result so that the most significant digit of the addition / subtraction result is the most significant digit of the normalized expression; Shift number redundant prediction means for predicting the number of digits from the most significant digit of the addition / subtraction to the most significant digit of the normalized expression within an error of n digits using the two binary operands; A shift error detecting means for detecting a difference between the most significant digit of the normalized expression and the most significant digit of the normalized expression as a result of the normalized shift; and performing a shift by an arbitrary number from 0 to n. Normalization shift correction means, wherein the shift number redundancy prediction means
Subtraction operation between two binary operands if
, One operand uses one's complement,
And an exclusive OR (XOR) signal for each digit and
Exclusive OR of the logical sum (OR) signal, and this signal is
Shifts the number of digits up to the first digit when viewed from the most significant digit
By making it a number, this is one digit for the exact shift number.
Is calculated within the error of, and the shift error correction is 0 or 1 digit
And the addition result by the addition / subtraction means is shifted by the normalization shift means using the prediction result of the shift number redundancy prediction means, and the shift result is calculated by the normalization shift using the shift error detection result. Shifted by the correction means,
A normalization device output as a normalization result. 2. An input of two normalized floating-point operands, comparison of the exponent parts of the two operands and calculation of the difference, and shifts the mantissa part of the operand having a small exponent part downward by the difference of the exponent part. Digit alignment means, addition or subtraction means for adding or subtracting two mantissa parts after digit alignment according to designation of addition or subtraction operation and the sign of the input operand; A normalizing shift means for shifting the entire result of addition / subtraction so that a digit comes to the most significant digit of the normalized expression; and, when the result of the normalized shift exceeds a predetermined number of digits in the normalized expression, rounds the result. A rounding means for reducing the number of digits in accordance with a mode; and two mantissas after the digit matching, the number of digits from the most significant digit of the result of the addition / subtraction to the most significant digit of the normalized expression. And a shift number redundant predicting means for predicting within an error of n digits by using a unit, wherein when the digit of the highest order as a result of the normalized shift is shifted from the most significant digit of the normalized expression, a shift error detecting means for detecting, and a normalization shift correction means for performing a shift from 0 in any number of n, the shift number of redundant predicting means, field addition operations
If the two mantissas after digit alignment are
In the case of ン, one of the mantissa parts after digit alignment uses 1's complement.
And an exclusive OR (XOR) signal for each digit.
Take the exclusive OR of the logical OR (OR) signal one digit lower,
Digits up to the first digit when this signal is viewed from the most significant digit
By making the number a shift number, this is the exact shift number
Is calculated within one digit error, and the shift error correction is 0
Alternatively, a one-digit shift is performed, and the addition result obtained by the addition / subtraction means is shifted by the normalization shift means using the prediction result of the shift number redundancy prediction means, and the shift result is obtained by using the shift error detection result. Shifted by the normalized shift correction means,
A normalization device output as a normalization result. 3. The method receives three floating-point operands represented by normalization, calculates the product of two operands, compares the third operand with the exponent part, and calculates the difference. The two mantissa parts after the multiply-accumulate operation are determined by the product-sum operation means for shifting the smaller mantissa part downward by the difference of the exponent part, by specifying the addition or subtraction operation, and by the sign of the input operand. Addition / subtraction means for adding or subtracting; normalization shift means for shifting the entire addition / subtraction result such that the one digit at the highest position of the addition / subtraction comes to the highest digit of the normalized expression; When the result exceeds a predetermined number of digits in the normalized expression, a rounding means for reducing the number of digits according to a rounding mode; and A shift number redundant predicting means for predicting the number of digits up to the current most significant digit within an error of n digits using the two mantissa parts after the product-sum operation; If the digit is shifted with the most significant digit of the normalized expression has a shift error detecting means for detecting the difference, and a normalization shift correction means for performing a shift from 0 in any number of n, the The shift number redundancy prediction means is used for the addition operation.
In this case, the two mantissa parts after the product-sum operation are subtracted
In the case of one, one of the mantissa parts after the product-sum operation uses one's complement.
And an exclusive OR (XOR) signal for each digit.
Take the exclusive OR of the logical OR (OR) signal one digit lower,
Digits up to the first digit when this signal is viewed from the most significant digit
By making the number a shift number, this is the exact shift number
Is calculated within one digit error, and the shift error correction is 0
Alternatively, a one-digit shift is performed, and the addition result obtained by the addition / subtraction means is shifted by the normalization shift means using the prediction result of the shift number redundancy prediction means, and the shift result is obtained by using the shift error detection result. Shifted by the normalized shift correction means,
A normalization device output as a normalization result.