JP2003029960A - Elimination of rounding step in short path of floating point adder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dual concurrent pipeline floating point adder unit shortening arithmetic delay time in a short path. SOLUTION: The device is provided with two concurrent data paths which are the short path and a long path. In the case that a floating point arithmetic operation is a subtraction operation and an exponent difference between two operands is 0, or in the case that the floating point arithmetic operation is the subtraction operation, the exponent difference is 1 and the mantissa of the operand having a larger exponent is within the range of a predetermined number, the short path is used so as to generate the result of the floating point arithmetic operation. In the case that the floating point arithmetic operation is addition operation, or in the case that the floating point arithmetic operation is the subtraction operation and the exponent difference is larger than 1, or in the case that the floating point arithmetic operation is the subtraction operation, the exponent difference is 1 and the mantissa of the operand having the larger exponent is within the range of a different predetermined number, the long path is used so as to generate the result of the floating point arithmetic operation.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to techniques for designing a floating point adder unit in a computer processor.

[0002]

Computer processors typically include a floating point adder for adding or subtracting two numbers (operands) in the form of floating point representations. In floating point representation, numbers are represented in the form ± m × R ^e , where m
Is a mantissa, R is a radix (or base), and e is an exponent. Typically, in floating point adders, the radix is implicitly defined, and a fixed number of bits is reserved for each of the floating point numbers. One bit of the fixed number of bits is reserved for the sign of the floating point number, a predetermined number of bits is reserved for the exponent, and a predetermined number of bits is the mantissa. Reserved for. The number of bits for the mantissa determines the precision of the floating point number, and the number of bits for the exponent determines the range of representable numbers. Therefore, the fixed bit format is a trade-off between precision and range.

Non-zero floating point numbers can be normalized by adjusting the mantissa and exponent values so that there is exactly one non-zero digit to the left of the decimal point in the mantissa. is there. Therefore, a leading bit of 1 is implicitly defined, to give one extra bit of data, or to double the representable mantissa.
It can be hidden. Furthermore, the radix is also typically implicitly defined and need not be represented in hardware. For example, I, which is incorporated herein by reference
In the 32-bit single precision format in the EEE-754 standard, the normalized floating point number N = ± m × R ^e can be stored as:

[Equation 1] Where S is a value related to the sign bit (S is 0 for positive numbers, S is 1 for negative numbers), E
Is an 8-bit value representing the exponent e greater than -127 (e is in the range -126 to +127), or E = e + 127, and F is a 23-bit value representing the fractional part of m. Is. Therefore, N = (− 1) ^S * 1. It is F * 2 ^E-127 .

Floating point addition operations are typically
(1) an exponential subtraction step to determine the amount of shift required to align the mantissas of the two operands, and (2) 10 of the two operands by right shifting the mantissa of the smaller operand. An alignment step for aligning the decimal points, (3) a mantissa addition or mantissa subtraction step for the actual arithmetic operation, and (4)
A transformation step to determine the sign of the resulting number, and (5) a leading 1 detection step to determine the amount of left or right shift required to normalize the resulting number. (6) a post-normalization step to normalize the resulting number and, in some cases, (7) the number of digits in the resulting number is the total number of digits allowed by the particular format. Rounding step in case of exceeding. The performance of the floating point adder unit can be slow if these many steps are performed sequentially.

The floating point adder unit can be improved by using dual parallel pipeline paths. Nhon T. Quach and Michael J. Flynn,
“An improved algorithm for high speed floating-po
int addition ”, Stanford Technical Report CSL-TR-9
See 0-442. FIG. 1 illustrates a conventional floating point adder unit having two parallel pipeline paths, short path (short path) 101 and long path (long path) 102, configured to perform floating point operations in parallel. Indicates 100. Although the floating point adder unit of FIG. 1 has potential speed advantages, it also requires a relatively complex hardware implementation for dual parallel pipeline paths.

[0006]

[Table 1]

Typically, in the conventional floating point adder unit of FIG. 1, each pipeline pass is configured so that it only requires a mantissa shift in one direction. Referring to FIG. 1, the short path is used for a valid subtraction operation when the difference between the exponents of two floating point operands is 0 or 1. Longpass is used for all add operations and for subtract operations when the exponent difference of two floating point operands is greater than one. This is summarized in Table I.

In the long pass, the mantissa is aligned by right shifting the smaller operand based on the exponential difference. The addition result in the long pass may need rounding, but since there is no leading zero, no left shift for post normalization is required. Rounding and at most one left shift may be required because the subtraction result in a long pass has at most one leading zero.

[0009]

[Table 2]

The exponent difference between the two operands is zero or one
, The short pass is used for the subtraction operation, so the mantissa alignment is limited to 1 bit, but a left shifter for normalization after subtraction may be required. is there. Furthermore, in shortpass some subtraction operations with an exponent difference of 1 may require rounding of the final result, but this rounding is typically done by an incrementer after the normalization operation. Done. This is summarized in Table II.

Protective bits, rounding bits, and / or sticky bits, as described in the IEEE-754 standard, are typically used to round the results of floating point operations. Referring now to Table II, the mantissas of the two operands need not be aligned if the exponent difference is zero. If the result of the mantissa subtraction is less than 1, the normalization step is performed using the normalization left shifter. No rounding of the result is required after this normalization step, as the guard bits, rounding bits and / or sticky bits are empty, as described in the IEEE-754 standard. If the exponent difference between the two operands is 1, then the mantissas of the two operands must be aligned by right shifting the mantissas of the smaller operands by one. Moreover, since the guard bits may not be empty for right shifts,
A rounding step may be required after mantissa subtraction.
If the protection bit has a value of 1, IEEE-75
Rounding operations need to be performed in order to obtain a 4 compliant result.

As an illustration, consider the following two operands with an exponent difference of 1 and a precision of 24 bits. A = 1.110000000000000000000000 * 2 ⁰ and B = 1.0000000000000000000000000001 * 2 ^-1 These two operands are subtracted by a short pass, which aligns the mantissa by right shifting the smaller operand B by one. To do. Mantissa A: 1.11000000000000000000000 Mantissa B: 0.10000000000000000000001 As a result of subtracting B from A, a number that needs rounding to remain within the range of 24-bit precision is obtained. Here, the unrounded result of the subtraction of B from A is AB = 1.001111111111111111111111, with the last bit being a guard bit. IEEE-
To comply with the H.754 standard, a rounding step may be required for a particular rounding mode if the guard bits have a value of 1, resulting in A
The rounded result of -B is 1.01000000000000000000000.

The rounding step in the short pass is typically done by an incrementer. This incrementer is undesirable because the delay due to the short path is potentially greater than the delay due to the long path as a result of this incrementer. Moreover, additional hardware (eg, logic gates) is required to implement the incrementer.

[0014]

Therefore, there is a need for improved dual parallel pipelined floating point adder technology.

[0015]

The apparatus and method of the present invention comprises:
Serves to perform floating point operations involving at least two operands in the form of floating point representations. This device includes two parallel data paths, a short path and a long path. Short pass is when the floating point operation is a subtraction operation and the difference between the exponents of the two operands (“exponential difference”) is 0, or the floating point operation is a subtraction operation and the exponent difference is 1 , And is used to produce the result of a floating point operation when the mantissa of the operand with the larger exponent is within a predetermined number range. Long pass is when the floating point operation is an addition operation, or when the floating point operation is a subtraction operation and the exponent difference is greater than 1, or the floating point operation is a subtraction operation, and Used to produce the result of a floating point operation when the exponent difference is 1 and the mantissa of the operand with the larger exponent is within another predetermined number. When using this logic in selecting the data path for floating point operations, the short path does not require such means as an incrementer for post subtraction normalization.

[0016]

DETAILED DESCRIPTION OF THE INVENTION The following detailed description is IEEE-7.
54 standard and includes many specific details of the floating point representation format in this standard to provide a thorough understanding of the invention. However, according to the present invention, the IEEE-75
It will be appreciated by those skilled in the art that it may be implemented outside the scope of the four standards and / or without these specific details.

The present invention includes a floating point adder system, method and algorithm. Some details of the preferred embodiments of the present invention are incorporated herein by reference, Ajay Naini, Atul Dhablania, Warren James.
And Debjit Das Sarma's paper “1-Ghz HAL SPAR
C 64 Dual Floating-point Unit With RAS Features ”,
^{Proceedings of the 15 th IEEE Symposium on} Compute
r Arithmetic, 11-13June 2001, Vail, Colorado, pp.
173-183.

FIG. 2 shows two floating point operands.

[Equation 2] 5 is a flow chart illustrating a process 200 of the present invention for performing an addition or subtraction operation on. Process 200
Includes an alignment step 210 and three parallel sub-processes: a short pass process 230, a long pass process 240 and a selection process 220. In the alignment step 210, the two operands are received and aligned in IEEE double precision format. Process 200 further includes a result selection step 250 for selecting a result from short pass process 230 or long pass process 240 based on the determination of selection process 220.

In one embodiment of the invention, the selection process uses a short pass process 230 for add or subtract operations based on the criteria set shown in Table III.
Or decide whether to select the result produced by the long pass process 240. Referring to Table III, 1. The operation is a subtraction operation and the operands A and B are
The difference between the indices of 0 is 0, or If the operation is a subtraction operation, the difference between the exponents of operands A, B is 1, and the mantissa of the operand with the larger exponent is less than 1.5, then the result from the short pass process 230 is Result selection step 250
Selected in.

[0020]

[Table 3]

Referring again to Table III, 1. If the operation is an addition operation, 1. The operation is a subtraction operation and the operands A and B are
2. If the difference between the indices of is greater than 1, or If the operation is a subtraction operation, the difference between the exponents of operands A and B is 1, and the mantissa of the operand with the larger exponent is greater than or equal to 1.5, then the result from longpass process 240 is the result. It is selected in the selection step 250.

[0022]

[Table 4]

In another embodiment, the selection process is based on Table IV
It is determined whether to select the result from the short pass process 230 or the long pass process 240 according to the criteria shown in. Referring to Table IV, as shown in this table: 1. The operation is a subtraction operation and the operands A and B are
The difference between the indices of 0 is 0, or If the operation is a subtraction operation, the difference between the exponents of operands A and B is 1, and the mantissa of the operand with the larger exponent is less than or equal to 1.5, then the result from short pass process 230 is Result selection step 250
Selected in.

Referring to Table IV, as shown in this table: 1. If the operation is an addition operation, 1. The operation is a subtraction operation and the operands A and B are
2. If the difference between the indices of is greater than 1, or If the operation is a subtraction operation, the difference between the exponents of operands A and B is 1, and the mantissa of the operand with the larger exponent is greater than 1.5, then the result from longpass process 240 is the result. Selection step 250
Selected in.

In one embodiment of the invention, the selection process 2
20 includes steps for determining whether the floating point operation is an addition or subtraction operation. In response to the determination that the operation is an addition operation, the selection process 20
0 decides to select the result from the longpass process 240 and sends this decision to the result selection step 250. On the other hand, in response to determining that the operation is a subtraction operation, selection process 200 proceeds to determine the exponent difference of the two operands. In response to determining that the exponent difference is greater than 1, the process 200 determines whether the longpass process 2
It decides to select the result from 40 and sends this decision to the result selection step 250. In response to determining that the exponent difference is zero, process 200 determines to select the result from shortpass process 230 and sends this decision to result selection step 250. In response to the determination in step 225 that the exponent difference is 1, the process 20
0 is the mantissa of the operand with the larger exponent 1.
Proceed to determine if it is less than 5 (or less than or equal to 1.5 if the selection rules of Table IV are used). Greater mantissa is less than 1.5 (or Table IV
Process 1.5 is less than or equal to 1.5 if the selection rule is used), the process 200 decides to select the result from the shortpass process 230, and this decision is taken as a result selection step 250. Send to. On the other hand, the mantissa of the operand with the larger exponent is greater than or equal to 1.5 (or 1.5 if the selection rules of Table IV are used).
Greater than or equal to) process 200.
Decides to select the result from the longpass process 240 and sends this decision to the result selection step 250.

The selection rules shown in Table III are easier to implement than the selection rules shown in Table IV. Table III
If the selection rule is used, then only the two MSB bits of the mantissa of the operand with the larger exponent are considered to have values whose mantissa is less than 1.5 (the result from the short path should be selected. It may be determined in step 227 to determine whether it has a value of (meaning) or a value greater than or equal to 1.5 (meaning that the result from the long pass should be selected).

FIG. 3 is a flow chart showing the short pass process 230 in more detail. Short pass process 23
At the beginning of 0, two sets of steps are performed in parallel with each other, and both sets of steps are followed by a normalization step 32.
A left shift for 4 is done. The first set of steps begins at step 310, where the two least significant exponent bits of operand A are 2 of operand B.
Compared to the two least significant exponent bits. 2 of operand A
In response to determining that the one least significant exponent bit is different from the two least significant exponent bits of operand B, an alignment and swap step 314 is performed later, in which step (314 The operand with the smaller exponent (based on the bits) is right-shifted by one bit to align the mantissas of the two operands, and the two operands are the exponents with the larger mantissas of the operands with the smaller exponents. May be swapped to be subtracted from the operands with. On the other hand, in step 310, the operand A 2
If it is determined that the one least significant exponent bit is the same as the two least significant exponent bits of operand B, then a mantissa comparison step 316 is performed to determine which mantissa is greater, and then A swap step 318 follows, which will swap the smaller mantissa so that it is subtracted from the larger mantissa. Either the alignment and swap step 316 or the swap step 318 is followed by the mantissa subtraction step 320, where the mantissa of the smaller operand is subtracted from the mantissa of the larger operand.

The second set of steps is the subtraction step 32.
It includes a leading zero prediction step 312 for predicting leading zeros in the final result of 0 and a leading zero counting step 322 for counting and encoding the predicted leading zeros. In the leading zero prediction step 312, the algorithm is used to generate _two leading zero vectors Z ₁ , Z ₂ . The leading zero vector Z ₁ is generated assuming that the mantissa of A is subtracted from the mantissa of B, and the leading zero vector Z ₂ is assumed that the mantissa of B is subtracted from the mantissa of A. Generated. Therefore, the second set of steps further comprises steps 310, 316.
A leading zero vector selection step 315 for selecting based on the result from, where the larger operand is determined and the mantissa of the smaller operand is determined from the mantissa of the larger operand. The assumption of being subtracted produces a leading zero vector.

For example, if it is determined in step 310 or step 316 that operand A is the larger operand, the leading zero vector Z ₂ is selected in leading zero selection step 315. In one embodiment of the invention, each of the mantissas of operands A, B has 52 bits, for example, m _A = (a ₅₁ a ₅₀ ...... a ₀ ) and m _B = (b ₅₁ b
₅₀ ...... b ₀ ). Assuming that m _A and m _B are aligned, the algorithm for generating Z ₂ performs its two's complement subtraction by reversing B, thereby

[Equation 3] Where :, +, and

[Equation 4] Indicates the AND operator, the OR operator, and the exclusive OR operator, respectively, and the overline indicates the NOT operator. The prediction algorithm described above, which does not use a full carry chain, uses the subtraction step 32.
When compared to the number of leading zeros in the final result of 0,
Prediction vector Z ₂ with one less number of leading zeros
To generate. Therefore, the short pass process further includes a leading zero correction step 330 to correct this error.

In a leading zero counting step 322, leading zeros in the selected leading zero vector are counted and encoded. In parallel with this, mantissa subtraction is calculated in subtraction step 320. Steps 312 and 31
Normalization step 324, since 5, 322 predicts the number of leading zeros, and thus the amount of left shift for normalization, and is performed in parallel with subtraction step 320.
It is possible that a left shift for ∘ is performed immediately after the subtraction step 320 according to the expected amount of shift. During the left shift for normalization step 324, the result from subtraction step 320 is left shifted according to the predicted number of leading zeros. A leading zero correction step 330 follows the left shift for the normalization step 324 to correct any resulting errors of the leading zero prediction algorithm for the leading zero prediction step 312.

Short pass does not require a rounding step because the result of the subtraction operation performed in the short pass always has a mantissa value less than or equal to 1. For example, the exponent difference has a value of 1, and the mantissa of the larger operand is 1.5.
If it is less than, then the minuend is in the range of (1,1.5) and the divisor reduced by 1 bit is [0.5,
Within the range of 1), the result included within the range of (0, 1) is obtained. If the result is less than one, the left shift for normalization step 324 moves the guard bit to at least the least significant bit position (LSB). Therefore, rounding is not necessary in the short pass.

FIG. 4 is a flow chart showing the longpass process 240 in more detail. Referring to FIG. 4, in response to the long path process being selected in step 210, both the lower bits of e ^A -e ^{B and} the lower bits of e ^B -e ^A are step 410a, 410b. Calculated in parallel for each. e ^A -e lower level bits of e ^A -e ^B, such as the two least significant bits of ^B, in step 412a, 0, 1, 2, or partially right mantissa only 3 bits operand B Used to shift, while the total result of e ^A -e ^B is step 41
Calculated in parallel in 1a. At the same time, e ^B
E ^B -e lower level bits of ^A, such as the two least significant bits of -e ^A, in step 412b, 0, 1,
It is used to partially right shift the mantissa of operand A by 2 or 3 bits, while the entire result of e ^B -e ^A is computed in parallel in step 411b.
Based on the total result of e ^A -e ^B or e ^B -e ^A , the smaller operand of A and B is selected at step 414 and the partially right-shifted smaller operand is stepped. 416 is selected. In addition, in step 416, the partially right-shifted smaller operand may be swapped with the other operand so that the smaller operand is in the reduced position for the subtraction operation. After step 416, step 4
20, followed by step 420, where the smaller operand may be further right shifted according to the overall result of e ^A -e ^B or e ^B -e ^A , which is always positive.
Since the data is shifted right from the mantissa of the smaller operand, rounding information is calculated in parallel at step 428, which performs rounding logic in accordance with the IEEE-754 standard.

In parallel with step 428, mantissa addition or subtraction is performed in steps 426 and 427. For proper IEEE-754 rounding, A + B, A + B + 1,
And the calculation of A + B + 2 is required. This calculation can be realized using only two parallel steps 424, 426 to generate A + B and A + B + 2 respectively, which is derived from A + B + 1 from these two results. This is possible because this derivation is done in step 430. At step 430, a first level result selection is further performed to select a result from the A + B, A + B + 1, and A + B + 2 results for the longpass process, the selected result from step 428. Normalized and / or rounded based on rounding information.

In the present invention, the subtraction operation on the exponent difference of 1 and the subtraction operation on the mantissa of the larger operand having a magnitude value of 1.5 or more are performed in the long pass. As mentioned above, in the long pass, the mantissas of the smaller operands are aligned by right shifting.
If the exponent difference is 1 and the mantissa of the larger operand has a value greater than 1.5, the subtraction is
Constrained to the subscripts in the range [1.5,2) and the subscripts in the range [0.5,1), the results are contained in the range (0.5,2). Therefore, a right shift after addition in the long pass is not needed and a potential single bit left shift may be processed during the first stage of the result selection step 430.

FIG. 5 is a schematic block diagram showing the overall structure of a floating point adder unit 500 implementing the process 200 described above. Referring to FIG. 5, the floating point adder unit 500 includes an alignment module 510 that implements the alignment step 210 in process 200. This registration module 510 receives as inputs the operands A, B for addition or subtraction and IE
Align the operands with the EE double precision format.

The floating point adder unit 500 has two parallel pipeline paths, a short path and a long path. In the short pass, the floating point adder unit 500 returns to step 31 of process 200.
Includes the exponential difference due to the "one" predictor 514-1 connected to the alignment module 510 for implementing a zero. In one embodiment of the present invention, the exponent difference by the "1" predictor 514-1 determines if the exponent difference in two operands is zero by examining only the two least significant exponent bits of each operand. To do. In addition, the floating point adder unit 500 includes a first swap module 5 connected to the alignment module 510 and the exponential difference provided by the "1" predictor 514-1.
Including 14. This first swap module 514
A circuit element implementing step 314 in process 200, that is, in response to determining that the exponent difference for operands A, B is non-zero by the exponent difference by the "1" predictor 514-1. Swap module 514 of 1 locates the mantissas of the two operands by right shifting the mantissas of the operands with the smaller exponent (as determined by examining only the two least significant exponent bits of each operand) by one bit. Match and swap the two operands if they happen to be in the minuend position. Furthermore, the floating point adder unit 5
00 is an operand comparison module 518-1 connected to the alignment module 510, a first swap module 514 and an operand comparison module 518-.
A second swap module 518 connected to
Including and If the exponent difference by the “1” predictor 514-1 determines that the exponent difference between the two operands is zero, the operand comparison module 518-1 and the second swap module 518 are the steps in process 200. 316, 318, that is, the operand comparison module 518-1 compares the mantissas of the two operands to determine which operand has the greater value, and the greater operand happens to occur. Is also a divisor, the second swap module 518 swaps the larger operand so that it is moved to the minuend position.

In addition, in the short pass, the floating point adder unit 500 uses the alignment module 51.
A leading zero prediction module 512 connected to 0,
Exponent difference and operand comparison module 518-1 and leading zero prediction module 5 by "1" predictor 514-1
12 and a selection module 515 connected to. Leading zero prediction module 512 performs step 312 of process 200 and selection module 515 performs step 315 of process 200. Leading zero prediction module 512 includes conventional logic circuitry configured to perform the logical operations dictated by the leading zero prediction algorithm for leading zero prediction step 310 of process 200, as described above.

Further, in the short pass, the floating point adder unit 500 is connected to the first adder 520 connected to the second swap module in pipeline stage 1 and the selection module 515. Leading zero counter 522 and left shifter 524 in the short path connected to the first adder and leading zero counter
Including and First adder 520 includes logic circuitry configured to perform mantissa subtraction step 320 in process 200. The leading zero counter performs the leading zero counting step 322 in process 200, and the left shifter 524 causes the normalizing step 324 in process 200.
Do a left shift for.

Further, in the short pass, floating point adder unit 500 includes a leading zero correction module 530 connected to left shifter 524 in pipeline stage 2. The leading zero correction module performs leading zero correction step 330 in process 200.

In the long pass, the floating point adder unit 500 includes a selection and alignment module 51.
It includes a second adder 511a and a third adder 511b both connected to 0. Operand A from the second adder 511a is aligned module 510 receives the B, a step 410a for calculating the lower level of the bits of e ^A -e ^B in the process 200, for all the results of e ^A -e ^B Step 411a for calculating the rest of the bits. The third adder 511b receives the operands A, B from the alignment module 510, step 410b for calculating the lower bits of e ^B -e ^A in process 200, and the total result of e ^B -e ^A. Step 411b for calculating the rest of the bits for
And do.

In the long pass, the floating point adder unit 500 further includes an alignment module 510.
And a first right shifter 513a connected to the second adder 511a and a selection and alignment module 510.
And a second right shifter 513b connected to the third adder 511b. The first right shifter 513a receives the operand A from the selection and alignment module 510.
B and receives the lower bits of e ^A -e ^B from the second adder 511a and sets the mantissa of the operand B to 0, 1, 2, or based on the lower bits of e ^A -e ^B. Step 412a for partially shifting right by 3 bits is performed. Similarly, the second right shifter 513a
Receives operands A, B from the selection and alignment module 510, and a third adder 511b to e ^B −.
receive the lower bits of e ^A , and e ^B −e ^A
Step 412b is performed to partially right shift the mantissa of operand A by 0, 1, 2, or 3 bits based on the lower bits of.

Further, in the long pass, the floating point adder unit 500 includes an operand selection module 517 connected to the second adder 511a and the third adder 511b, a first right shifter 513a and a first right shifter 513a. Includes a select / swap module 516 connected to a second right shifter 513b and an operand select module 517. Operand selection module 517 processes 20
Perform step 414 at 0, i.e., the operand selection module selects the smaller operand between operands A and B based on the result of the second adder 511a and / or the third adder 511b. This selection is output to the selection / swap module 516,
Select / swap module 516 performs step 416 of process 200 by selecting the partially right-shifted mantissa of the smaller operand between the partially right-shifted mantissas of A, B. further,
If it is a subtraction operation and the smaller operand happens to be the minuend, the selection / swap module 51
6 swaps the two operands so that the smaller operand is moved to the reduced position.

Further, in the long pass, the floating point adder unit 500 has a third right shifter 521 and a third right shifter 521 connected to the operand selection module 514 and the selection / swap module 516.
3-2 carry save adder (CSA) 5 connected to
23, a fourth adder 525 connected to the 3-2CSA 523, and a fifth adder 526 connected to the third right shifter 521. Third right shifter 5
21 is the right shift step 42 in the process 200.
0, and the second adder 511a or the third adder 5
Shift the partially shifted mantissa of the smaller operand based on the higher bits of the result of 11b. The fourth adder 525 determines A in process 200.
Perform step 424 to calculate + B + 2, and
The adder 526 of 1 performs step 426 for calculating A + B in process 200. 3-2CSA is
Since the LSB position is different between double precision and single precision, it is used for generating A + B + 2.

In the long pass, the floating point adder unit 500 further includes a rounding logic module 528 connected to the second right shifter 520. Since the data is right-shifted from the mantissa of the smaller operand in the second right shifter 520, IEEE-754
As described in the standard, LSB + 1 bit and L
Rounding information, including SBs, guard bits, rounding bits, and sticky bits are calculated in parallel by rounding logic module 528.

Further, in the long pass, the floating point adder unit 500 includes a fourth adder 524 and a fifth adder 524.
A first-stage result selection module 531 connected to the adder 526 and the rounding logic module 528. The first stage result selection module 531 performs the first stage result selection step 430 in the process 200. Figure 6A
Is a table containing the result selection criteria and rounding and normalization algorithms used by the first stage result selection module 531 for addition operations. FIG. 6B is a table containing the result selection criteria and rounding and normalization algorithms used by the first stage result selection module 531 for subtraction operations.

As shown in FIG. 6A, the rounding and normalization performed by the first stage result selection module is based on the overflow bit, which is the most significant bit (MSB) of the selected result. , Round bit, and 1 bit position higher than LSB. Rounding bit is IEEE for all rounding modes
FIG. 6 shows the conditional increment of the pre-normalized result for rounding according to E-754, and IEEE-75
Rounding mode, sign, protection bit,
Calculated based on rounding bits, sticky bits, and / or overflow bits.

Referring to the table of FIG. 6B, the range (0.5,
The subtraction result contained within 2) will require a 1-bit left shift for normalization if the result is less than one. In this case, the rounding position would change from LSB to guard bit. These two possible positions can be processed using two fill bits at the LSB + 1 and LSB positions combined with the A + B and A + B + 2 results. For example, if the LSB and guard bit are both 1, then rounding up will occur, reflected by the selection of A + B + 2 in the higher bits, which will zero the LSB bit in the process. Further details on how fill bits are combined with A + B and A + B + 2 results to produce a result for a long pass are included in FIG. 6B. The rounding algorithms shown in the table of FIG. 6A and the table of FIG. 6B support all four rounding modes as described in the IEEE-754 standard.

Referring to FIG. 5, the floating point adder unit 500 further includes a selection logic module 540, which is connected to the alignment module and performs the selection process 220. A logic circuit configured, i.e. configured to determine whether to select a result from a short path or a long path based on the selection criteria in Table III or Table IV. The floating point adder unit 500 further includes a result selection module 550 connected to the left shifter 524 in the short path and the first stage result selection module 531 in the long path and the selection logic module 540. The result selection module 550
Configured to perform result selection step 250 within process 200, ie, selection logic module 54.
A logic circuit configured to select a result between a short path result and a long path result based on a determination from zero.

[0049]

The present invention reduces hardware costs by eliminating the incrementer in pipeline stage 3 in the short path of the conventional adder shown in FIG.

The present invention further eliminates the time delay associated with the rounding step in the short path of conventional floating point adders.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional floating point adder unit with parallel pipeline paths.

FIG. 2 is a flow diagram illustrating a process for performing add or subtract operations on two floating point operands according to one embodiment of the invention.

FIG. 3 is a flow diagram illustrating a short pass process in a process for performing add or subtract operations on two floating point operands according to one embodiment of the invention.

FIG. 4 is a flow diagram illustrating a long pass process in a process for performing add or subtract operations on two floating point operands according to one embodiment of the invention.

FIG. 5 is a schematic block diagram of a floating point adder unit with two parallel data paths according to the present invention.

6A is a table including criteria for selecting an addition result in a long pass of a floating point adder unit according to the present invention, and FIG. 6B is a long pass of a floating point adder unit according to the present invention. FIG. 6 is a table diagram including criteria for selecting a subtraction result in FIG.

[Explanation of symbols]

200 ... Process 210 ... Positioning step 220 ... Selection process 230 ... Short pass process 240 ... Long pass process 250 ... Result selection step 312 ... Leading zero prediction step 314 ... Alignment and swap steps 315 ... Leading zero vector selection step 316 ... Mantissa comparison step 318 ... Swap step 320 ... Mantissa subtraction step 322 ... Leading zero calculation step 324 ... Normalization step 330 ... Leading zero correction step

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Atatur Dabulania             United States, California 95138,             San Jose, Glenniegles Drive             5817 (72) Inventor Warren James             United States, California 95128,             San Jose, Pamler Avenue 591 F term (reference) 5B016 AA01 AA02 BA04 BB02 CA01                       CD01

Claims (10)

[Claims] 1. A floating point adder having a long path and a short path, each having a mantissa and an exponent.
Selecting a path for a subtraction operation including two operands, selecting the long path in response to a difference between exponents of the two operands being greater than one; Selecting the short path in response to a difference between the exponents of the operands being zero, and the operand having a difference between the exponents of the two operands being 1 and having a greater exponent In response to the mantissa of being within the range of the first predetermined number,
The difference between selecting the short path and the exponent of the larger operand and the exponent of the smaller operand is 1, and the mantissa of the larger operand is a second predetermined number. Selecting the long path in response to being within the range of. 2. The first predetermined number range comprises a number less than 1.5 and the second predetermined number range comprises a number greater than or equal to 1.5. The method according to Item 1. 3. The first predetermined number range consists of numbers less than or equal to 1.5, and the second predetermined number range consists of numbers greater than 1.5. The method of claim 1. 4. A floating point adder unit having two parallel data paths, a short path and a long path, each producing a result for a floating point operation including two operands each having a mantissa and an exponent. A method of selecting a result between a result produced by a short pass and a result produced by the long pass, in response to the floating point operation being an addition operation,
In response to selecting the result produced by the long pass, and in response to the floating point operation being a subtraction operation and the difference between the exponents of the two operands being greater than 1; In response to selecting the generated result and in which the floating point operation is a subtraction operation and the difference between the exponents of the two operands is zero. Selecting the result, the floating point operation being a subtraction operation, the difference between the exponents of the two operands being 1, and the mantissa of the operand having a larger exponent being a first predetermined. Selecting the result produced by the short path in response to being within a range of a predetermined number, and the floating point operation being subtracted. Arithmetic, the difference between the exponents of the two operands is 1, and the mantissa of the operand with a greater exponent is within a second predetermined number, Selecting the result caused by the long pass. 5. The first predetermined range of numbers comprises less than 1.5 and the second predetermined range of numbers comprises greater than or equal to 1.5. Item 4. The method according to Item 4. 6. The first predetermined range of numbers consists of numbers less than or equal to 1.5 and the second predetermined range of numbers consists of numbers greater than 1.5. The method of claim 4. 7. A floating point adder unit comprising a short pass and a long pass, said short pass comprising no means for rounding the subtraction result. 8. A floating point adder unit for performing a floating point operation on two operands, each of which receives said two operands and is capable of occurring with respect to said floating point operation comprising said two operands. Two parallel data paths, a short path and a long path, that produce a result, and the short as a result of the floating point operation using the method of any of claims 3, 4 or 5. Selection logic running in parallel with each of the data paths including logic circuitry configured to determine whether to select the probable result from a path or the probable result from the long path. Floating point adder unit including module and. 9. A result selection module further comprising a result selection module connected to said short path, said long path and said selection logic module, and the result of said floating point operation based on said decision made by said selection logic module. 8. The floating point adder unit of claim 7, including a logic circuit configured to select between the possible result from the short path and the possible result from the long path. 10. The floating point adder unit of claim 8, wherein the short path does not include means for rounding the subtraction result.