KR100433627B1 - Low power multiplier for complex numbers - Google Patents

Abstract

The present invention discloses a complex multiplier that computes the product of two complex numbers x = x ₀ + j x ₁ and y = y ₀ + j y ₁ . It disclosed a complex multiplier multiplying the imaginary part (y ₁₎ of the x of the real part (x ₀₎ and y of a real part (y ₀₎ for multiplying the first multiplier and the imaginary part (x ₁₎ of the x to the y A second multiplier for operation, a third multiplier for multiplying the real part (x ₀ ) of x and an imaginary part (y ₁ ) of y, an imaginary part (x ₁ ) of x and a real part (y ₀ ) of y A fourth multiplier for multiplying, a subtractor for calculating a difference between output values of the first and second multipliers, calculating a real part of a complex product, and calculating a sum of output values of the third and fourth multipliers, An adder for calculating an imaginary part, a comparator comparing whether the real part (x ₀ ) of x and the imaginary part (x ₁ ) and / or the real part (y ₀ ) of y and the imaginary part (y ₁ ) of y are the same, respectively, And when the real part and the imaginary part of the two complex inputs are equal to each other according to the result of the comparator, the output values of the first and second multipliers enter the adder. Selected such that it includes a.

Description

Low power multiplier for complex numbers

The present invention relates to a multiplier for calculating two complex numbers consisting of a real part and an imaginary part, and more particularly, to a multiplier operating at low power.

With the development of technology, in particular with the development of semiconductor technology, high-speed processing of large-capacity multimedia data is increasingly required, and circuits that perform various operations are gradually increasing in speed and low power. As a representative example of such a circuit, a multiplier and an adder or a subtracter for real or complex numbers may be used. In particular, a plurality of complex multipliers are used in wired and wireless communication systems, signal processing and image processing systems, and the like. .

Here, with reference to FIG. 1, the conventional complex multiplier is demonstrated.

In general, complex numbers x and y are represented by x ₀ + jx ₁ and y ₀ + jy ₁ , and their products ( x · y) are expressed by the following equation.

xy = (x ₀ + jx _One ) (y ₀ + jy _One )

= (x ₀ y ₀ -x _One y _One ) + j (x ₀ y _One + x _One y ₀ )

= A + jB = z

In that way, performing such a complex multiplier two complex inputs, x = x ₀ + jx ₁ and y = y ₀ + j y x of the real part multiplication of x ₀ and y of the real part of y ₀ for ₁ claim The first multiplier 101 and the outputs of the second multiplier 102 and the first and second multipliers 101 and 102 that perform a multiplication operation of the imaginary part x ₁ of x and the imaginary part y ₁ of y are received. And a subtractor 105 to find the difference between the two multipliers 101 and 102. At this time, the output of the subtractor 105 corresponds to the real part (a) of z, which is the product of two complex numbers x and y.

In addition, the complex multiplier performs a multiplication operation of the third multiplier 103 which performs the multiplication operation of the real part x ₀ of x and the imaginary part y ₁ of y, and the real part y ₀ of the imaginary part x ₁ and y of x. And an adder 106 that receives the outputs of the fourth multiplier 104 and the outputs of the third and fourth multipliers 103 and 104 to obtain a sum of the third and fourth multipliers 103 and 104. At this time, the output of the adder 106 corresponds to the imaginary number b of z, which is the product of two complex numbers x and y.

However, in the conventional complex multiplier, when the real part (x ₀ or y ₀ ) and the imaginary part (x ₁ or y ₁ ) are the same in the complex number x or y, only the first and second multipliers 101 and 102 are used for complex numbers. Although the product can be obtained, the third and fourth multipliers 103 and 104 are operated unnecessarily. This results in unnecessary power consumption.

The present invention provides a complex multiplier capable of reducing power consumption by designing only an optimal multiplier required for operation when the real part and the imaginary part of two input complex numbers are the same.

1 is a block diagram illustrating a general complex multiplier.

2 is a block diagram of a complex multiplier according to the present embodiment.

3 is a block diagram illustrating a comparator comparing the real and imaginary parts of the complex numbers of FIG. 2.

(Explanation of symbols for the main parts of the drawing)

201: first multiplier 202: second multiplier

203: third multiplier 204: fourth multiplier

205: Subtractor 206: Adder

300: selection unit

In order to achieve the technical problem of the present invention, the present invention, in the complex multiplier for calculating the product of two complex numbers x = x ₀ + j x ₁ and y = y ₀ + j y ₁ , the real part of the x ( x ₀ ) and a first multiplier that multiplies the real part y ₀ of y, a second multiplier that multiplies the imaginary part x ₁ of y and the imaginary part y ₁ of y, and x A third multiplier for multiplying the real part (x ₀ ) and the imaginary part (y ₁ ) of y, and a fourth multiplier for multiplying the imaginary part (x ₁ ) of y and the real part (y ₀ ) of y A subtractor for calculating a difference between output values of the first and second multipliers, calculating a real part of a complex product, an adder for calculating an imaginary part of a complex product, calculating a sum of the output values of the third and fourth multipliers, a real part of said x (x ₀₎ and the imaginary part (x ₁₎ and / or the real part of y (y ₀₎ and the imaginary part of y (y _1), the same comparator, and the comparator for comparing whether each According to the result of the present invention, if at least one of the real part and the imaginary part of the two complex input is the same, and includes a selection unit for inputting the output values of the first and second multipliers to the adder.

The selector includes: a first multiplexer which sends an output of a first multiplier to an adder when any one of the complex real part and the imaginary part is the same; A second multiplexer for outputting an output of a second multiplier when the complex real and imaginary parts are the same; If both the real and imaginary parts of the two complex numbers are the same, a third multiplexer for sending the output of the first multiplier to the adder may be included.

The second, third and fourth multipliers are configured to supply power to each multiplier when the real part and the imaginary part of the two complex numbers x = x ₀ + j x ₁ and y = y ₀ + j y ₁ are the same. The switch further includes a switch 211, 212, 213.

According to the present invention, when the real part and the imaginary part of two complex inputs are the same, the same function as that of the conventional complex multiplier is provided by properly shutting off the power supply of the second, third and fourth multipliers inside the complex multiplier and sharing the remaining multiplier outputs. And operating speed but has the advantage of reducing power consumption.

(Example)

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements.

2 is a block diagram illustrating a complex multiplier according to the present invention, and FIG. 3 is a block diagram illustrating a comparator comparing a real part and an imaginary part of the complex number of FIG. 2.

Referring to FIG. 2, the multiplier for calculating the product of the complex numbers x = x ₀ + j x ₁ and y = y ₀ + j y ₁ of the present invention is a product of the real part x ₀ of x and the real part y ₀ of y. A first multiplier 201 for calculating, an imaginary part x ₁ of x and an output of the second multiplier 202 for calculating the product of the imaginary part y ₁ of y , and the first and second multipliers 201 and 202 are received. And a subtractor 205 for obtaining the difference between the outputs of the second multipliers 201 and 202. Here, the subtractor 205 outputs "A" which is the real part of the product z of the two complex numbers x and y.

Further, the complex multiplier of the present invention calculates the product of the third multiplier 203 for calculating the product of the real part x ₀ of x and the imaginary part y ₁ of y , and the product of the real part y ₀ of the imaginary part x ₁ of y and y. A fourth multiplier 204.

Here, the second, third, and fourth multipliers 202, 203, and 204 are selectively operated by a power supply V _D according to the operations of the first, second, and third switches 211, 212, 213. In this case, the first switch 211 of the second multiplier 202 is turned on / off according to the second control signal s ₁ , and the second and third switches of the third and fourth multipliers 203 and 204 ( 212 and 213 are turned on / off according to the first control signal s ₀ . In the present embodiment, if the first and second control signals s ₀ and s ₁ are "0", the second to fourth multipliers are operated, and if it is "1", they are designed not to operate.

The selector 300 includes a first multiplexer 207 to which the outputs of the first and third multipliers 201 and 203 are input and controlled by the first control signal s ₀ , and the second and fourth multipliers 202 and 204. Is the input of the second multiplexer 208, controlled by the first control signal s ₀ , and the output of the first multiplexer 207 and the output of the second multiplexer 208. And a third multiplexer 209 controlled by the second control signal s ₁ .

The first and second multiplexers 207 and 208 may optionally include a first input (D1: output of the third or fourth multiplier) or a second input (D2: first or second) according to the first control signal s ₀ . 2 multiplier output). In this case, when the first control signal s ₀ is "0", the first and second multiplexers 207 and 208 output a first input (D1: output of the third or fourth multiplier) and control the first control. When the signal s ₀ is "1", the second input D2 (output of the first or second multiplier) is output. In addition, the third multiplexer 209 may optionally include a first input (D1: output of the first multiplexer) or a second input (D2: output of the second multiplexer) according to the output signal s ₁ of the comparator 214. Outputs At this time, the third multiplexer 209 outputs a first input (D1: output of the first multiplexer) when s ₁ is "0", and a second input D2 when s ₀ is "1". : Output of the second multiplexer).

Table 1 below illustrates the outputs Q of the first, second and third multiplexers 207, 208 and 209 according to the first and second control signals s ₀ and s ₁ .

Output input Q s ₀ or s ₁ = 0 D1 s ₀ or s ₁ = 1 D2

In this case, the signals applied to the first, second and third switches 211, 212, 213 and the first, second, and third multiplexers 207, 208, 209, that is, the control signals s ₀ , s ₁ , are determined in the following manner. do.

That is, as shown in FIG. 3, the comparator 214 compares the real part (x ₀ or y ₀ ) of the complex number x, y and the imaginary part (x ₁ or y ₁ ). At this time, the result of comparing the real part (x ₀ ) of the complex number x and the imaginary part (x ₁ ) and the real part (y ₀ ) and the imaginary part (y ₁ ) of the complex number y is the first control signal (s ₀ ) and the first. 2 corresponds to the control signal s ₁ . The attached Table 2 and Table 3 are the first and second control signals (s _0, s ₁₎ according to the comparative complex number x, y of the real part (x ₀ or y ₀₎ and the imaginary part (x ₁ or y ₁₎ Table shown.

Output / input s ₀ x ₀ = x ₁ or y ₀ = y ₁ One Otherwise 0

Output / input s ₁ x ₀ = x ₁ and y ₀ = y ₁ One Otherwise 0

The outputs Q of the first and third multiplexers 207 and 209 are input to the adder 206, respectively, and output B, an imaginary part of the multiplication value z of two complexes x and y.

The operation of the complex multiplier of the present invention having such a configuration will be described.

First, the real part and the imaginary part of complex numbers x and y are not the same ( x ₀ ? X ₁ , y ₀ ? Y ₁ ).

In this case, the first multiplier 201 and the second multiplier 202 operate normally as in the prior art, and the subtractor 205 obtains the output value "A".

On the other hand, since the real part and the imaginary part of complex numbers x and y are not the same, the control signals s ₀ and s _{1 which} are output signals of the comparator 214 become "0". The first, second, and third switches 211, 212, 213 are turned on, and accordingly, the second, third, and fourth multipliers 202, 203, 204 are operated to perform a multiplication operation. The two multiplexers output the outputs of the third and fourth multipliers 203 and 204, respectively, and the third multiplexer 208 outputs the results of the fourth multiplier. Accordingly, the adder 206 obtains the output value "B".

On the other hand, if any one of the real part and the imaginary part of the complex number x, y is the same ( x ₀ = x ₁ or y ₀ = y ₁ ), it operates as follows.

In this case, the first multiplier 201 and the second multiplier 202 operate normally as in the prior art, and the subtractor 205 obtains the output value "A".

On the other hand, since any one of the real part and the imaginary part of the complex number x, y is the same, the output signals of the comparator 214, that is, the first and second control signals s _{0 and} s ₁ are respectively " 1 ""Becomes. Then, the third and fourth multipliers 203 and 204 are powered off and do not operate. Further, the output of the first multiplexer 207 is the output (x ₀ y ₀ ) of the first multiplier 201, and the output of the second multiplexer 208 is the output (x ₁ ) of the second multiplier 202. y ₁ ), and the output of the third multiplexer 209 becomes the output (x ₁ y ₁ ) of the second multiplexer 208, that is, the output of the second multiplier. Accordingly, the outputs of the first and second multipliers 201 and 202 are applied to the adder 206. Accordingly, when the real part and the imaginary part of the complex numbers x and y are the same, the power of the third and fourth multipliers 203 and 204 by the first and second control signals s ₀ and s ₁ which are outputs of the comparator 214. The imaginary part "B" of the product z of complex numbers x and y is calculated only by the output of the 1st and 2nd multipliers 201 and 202.

In addition, when the real part and the imaginary part of complex numbers x and y are the same ( x ₀ = x ₁ = y ₀ = y ₁ ), the following operation is performed.

In this case, the first multiplier 201 and the second multiplier 202 operate normally as in the prior art, and the subtractor 205 obtains the output value "A".

On the other hand, since both the real part and the imaginary part of the complex numbers x and y are the same, the output signals of the comparator 214, that is, the first and second control signals s ₀ and s ₁ are both "1". Then, the second, third and fourth multipliers 202, 203 and 204 are powered off and do not operate. Further, the output of the first multiplexer 207 is the output (x ₀ y ₀ ) of the first multiplier 201, and the output of the second multiplexer 208 is the output (x ₁ ) of the second multiplier 202. y ₁₎ it is, but the third output of the multiplexer 209 is the output (x ₀ y ₀₎ of the output (x ₀ y _0), that is, a first multiplier 201, a first multiplexer (208) . Therefore, the output of the first multiplier 201 is simultaneously applied to both inputs of the adder 206. Accordingly, when both the real part and the imaginary part of the complex number x, y are the same, the second, third and fourth multipliers (i.e., by the first and second control signals s ₀ and s ₁ , which are outputs of the comparator 214). The power of 202, 203 and 204 is cut off, and the imaginary part "B" of the product z of complex x and y is calculated only by the output of the first multiplier.

As described in detail above, according to the present invention, when the real part and the imaginary part of one or more complex inputs of the two complex inputs are the same, the same functions as those of the conventional complex multiplier are turned off by cutting off the power of some multipliers and sharing the remaining multiplier outputs. It has the speed of operation but has the advantage of reducing power consumption.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (4)

For a complex multiplier that computes the product of two complex numbers x = x ₀ + j x ₁ and y = y ₀ + j y ₁ , A first multiplier for multiplying the real part (x ₀ ) of x and the real part (y ₀ ) of y; A second multiplier for multiplying the imaginary part (x ₁ ) of x and the imaginary part (y ₁ ) of y; A third multiplier for multiplying the real part (x ₀ ) of x and the imaginary part (y ₁ ) of y; A fourth multiplier for multiplying the imaginary part (x ₁ ) of x and the real part (y ₀ ) of y; A subtractor for calculating a real part of a complex product by calculating a difference between output values of the first and second multipliers; An adder for calculating a imaginary part of a complex product by calculating a sum of output values of the third and fourth multipliers; A comparator for comparing the real part x of the (x ₀₎ and the imaginary part (x ₁₎ and / or the real part of y (y ₀₎ and the imaginary part (y ₁₎ of the same if y respectively; And And a selector for inputting the output values of the first and second multipliers to the adder when at least one of the real part and the imaginary part of the two complex inputs is the same according to the result of the comparator. The method of claim 1, The selection unit, A first multiplexer for applying an output value of a first multiplier to an adder when the complex real part and the imaginary part are the same; A second multiplexer for applying an output value of a second multiplier to a third multiplexer when the complex real part and the imaginary part are the same; And a third multiplexer for sending the output of the first multiplier output from the first multiplexer to an adder when both the real and imaginary parts of the two complex numbers are the same. The method according to claim 1 or 2, The second, third and fourth multipliers further include a switch for shutting off a multiplier when the real part and the imaginary part of the two complex numbers x = x ₀ + j x ₁ and y = y ₀ + j y ₁ are the same. Complex multiplier, characterized in that it comprises. The method of claim 3, wherein And the comparator outputs a first, second and third multiplexer and a control signal (s ₀ , s ₁ ) for controlling a power cutoff switch of the second, third and fourth multipliers.