JPH04332036A - Floating decimal point multiplier and its multiplying system - Google Patents

Floating decimal point multiplier and its multiplying system

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Publication number
JPH04332036A
JPH04332036A JP3102278A JP10227891A JPH04332036A JP H04332036 A JPH04332036 A JP H04332036A JP 3102278 A JP3102278 A JP 3102278A JP 10227891 A JP10227891 A JP 10227891A JP H04332036 A JPH04332036 A JP H04332036A
Authority
JP
Japan
Prior art keywords
total
multiplier
output
decimal point
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3102278A
Other versions
JP3345894B2 (en
Inventor
Yasuhiko Hagiwara
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP10227891A priority Critical patent/JP3345894B2/en
Publication of JPH04332036A publication Critical patent/JPH04332036A/en
Application granted granted Critical
Publication of JP3345894B2 publication Critical patent/JP3345894B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

Links

Abstract

PURPOSE: To improve operating speed by constituting a multiplier for the mantissa part of a signed binary adder tree and a subtractor and finding out the total logical sum of cut-off bits from the output of the signed binary adder.
CONSTITUTION: The exponential parts E1, E2 of a floating decimal point segmented in the preprocessing stage are mutually added by an exponential part adder 1. The mantissa parts M1, M2 consisting of (n) bits in the floating decimal point are multiplied by each other by a multiplier 2. The total OR H of outputs D, F respectively corresponding to about lower (n) bits of each of the outputs B, C of the signed binary adder tree 21 is found out by an OR circuit 3. A rounding digit positioning device 4 outputs the output I of the floating decimal point multiplier based upon the output A of the adder 1 and the upper bits G of the output of the multiplier 2 by using the total OR H as a control signal. Since total delay time = preprocessing + multiplication + rounding digit positioning is formed, the operation time can be shortened only by the calculation time of the total OR.
COPYRIGHT: (C)1992,JPO&Japio
JP10227891A 1991-05-08 1991-05-08 Floating point multiplier Expired - Lifetime JP3345894B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10227891A JP3345894B2 (en) 1991-05-08 1991-05-08 Floating point multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10227891A JP3345894B2 (en) 1991-05-08 1991-05-08 Floating point multiplier

Publications (2)

Publication Number Publication Date
JPH04332036A true JPH04332036A (en) 1992-11-19
JP3345894B2 JP3345894B2 (en) 2002-11-18

Family

ID=14323139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10227891A Expired - Lifetime JP3345894B2 (en) 1991-05-08 1991-05-08 Floating point multiplier

Country Status (1)

Country Link
JP (1) JP3345894B2 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007215192A (en) * 2006-02-09 2007-08-23 Altera Corp Specialized processing block for programmable logic device
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9063870B1 (en) 2006-12-05 2015-06-23 Altera Corporation Large multiplier for programmable logic device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9395953B2 (en) 2006-12-05 2016-07-19 Altera Corporation Large multiplier for programmable logic device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007215192A (en) * 2006-02-09 2007-08-23 Altera Corp Specialized processing block for programmable logic device
US9395953B2 (en) 2006-12-05 2016-07-19 Altera Corporation Large multiplier for programmable logic device
US9063870B1 (en) 2006-12-05 2015-06-23 Altera Corporation Large multiplier for programmable logic device
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit

Also Published As

Publication number Publication date
JP3345894B2 (en) 2002-11-18

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