JPS6156823B2 - - Google Patents
Info
- Publication number
- JPS6156823B2 JPS6156823B2 JP55126798A JP12679880A JPS6156823B2 JP S6156823 B2 JPS6156823 B2 JP S6156823B2 JP 55126798 A JP55126798 A JP 55126798A JP 12679880 A JP12679880 A JP 12679880A JP S6156823 B2 JPS6156823 B2 JP S6156823B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- time
- multiplication
- real part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010977 unit operation Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/4806—Computations with complex numbers
- G06F7/4812—Complex multiplication
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Description
【発明の詳細な説明】
この発明は、高速フーリエ変換器のような複素
数を取り扱うデイジタル演算装置における乗算装
置の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a multiplication device in a digital arithmetic device that handles complex numbers, such as a fast Fourier transformer.
この種の演算装置としては、従来、第１図に示
すものがあつた。図において、１と２は被乗数の
実数部ａと虚数部ｂの入力端子、３と４は乗数の
実数部ｃと虚数部ｄの入力端子、５と６は積の実
数部Ａと虚数部Ｂの出力端子、７〜１０は上記ａ
とｃ、ｂとｄ、ａとｄ、ｂとｃの乗算を行なう乗
算回路、１１は、acよりbdを減算する減算回
路、１２はadとbcを加算する加算回路、１３と
１４は単位演算時間間隔で減算回路出力と加算回
路出力をそれぞれラツチして、複素数の積を出力
するラツチ回路である。 As this type of arithmetic device, there has conventionally been one shown in FIG. In the figure, 1 and 2 are input terminals for real part a and imaginary part b of the multiplicand, 3 and 4 are input terminals for real part c and imaginary part d of the multiplier, and 5 and 6 are input terminals for real part A and imaginary part B of the product. output terminals, 7 to 10 are the above a
11 is a subtraction circuit that subtracts bd from ac, 12 is an addition circuit that adds ad and bc, 13 and 14 are unit operations. This is a latch circuit that latches the output of the subtraction circuit and the output of the addition circuit at time intervals and outputs the product of complex numbers.
つぎに動作について説明する。複素数の乗算は
つぎの式(1)に示す公式にしたがつて演算すればよ
い。 Next, the operation will be explained. Multiplication of complex numbers can be performed according to the formula shown in equation (1) below.
（ａ＋jb）×（ｃ＋jd）
＝（ac−bd）＋ｊ（ad＋bc）＝Ａ＋jB ……(1)
ここでａ：被乗数の実数部
ｂ：被乗数の虚数部
ｃ：乗数の実数部
ｄ：乗数の虚数部
Ａ：積の実数部
Ｂ：積の虚数部
入力端子１〜４より入力された被乗数と乗数の
実数部ａとｃ、および虚数部のｂとｄは、乗算回
路７〜１０で式１にしたがつて、乗算されて、積
ac、bd、ad、bcを得る。減算回路１１では、積
acから積bdを減じて差ac−bdを出力する。加算
回路１２では、積adと積bcとを加えて和ad＋bc
を出力する。ラツチ回路１３と１４ではそれぞ
れ、差ac−bdと和ad＋bcを装置に備わつている
タイミングによりラツチし、複素数の積の実数部
Ａと虚数部Ｂを出力し、複素数の積出力Ａ＋jB
を得る。(a + jb) × (c + jd) = (ac - bd) + j (ad + bc) = A + jB ... (1) where a: Real part of the multiplicand b: Imaginary part of the multiplicand c: Real part of the multiplier d: Imaginary part of the multiplier A: Real part of the product B: Imaginary part of the product The real parts a and c of the multiplicand and multiplier input from input terminals 1 to 4, and the imaginary parts b and d, are expressed as Formula 1 in multiplication circuits 7 to 10. are multiplied, and the product is
Get ac, bd, ad, bc. In the subtraction circuit 11, the product
Subtract the product bd from ac and output the difference ac - bd. The adder circuit 12 adds the product ad and the product bc to obtain the sum ad+bc.
Output. The latch circuits 13 and 14 respectively latch the difference ac-bd and the sum ad+bc according to the timing provided in the device, output the real part A and the imaginary part B of the product of complex numbers, and output the product output of complex numbers A+jB.
get.
ここで乗算回路７〜１０の回路素子等について
は種々知られているところであるが、回路の規
模、消費電力が他の構成回路素子より大であるこ
とは一般的に良く知られている。 Although various information is known about the circuit elements of the multiplier circuits 7 to 10, it is generally well known that the scale and power consumption of the circuits are larger than that of other constituent circuit elements.
上述のように、従来の乗算装置においては、複
素数の乗算を４つの乗算回路と、１つの減算回路
と、１つの加算回路とにより実現しているが、高
速フーリエ変換器等においては、第１図に示した
ような複素数の乗算装置を複数個用いているの
で、結局多数の乗算回路が使用されることとな
り、回路の規模および消費電力が増大する。 As mentioned above, in conventional multiplication devices, multiplication of complex numbers is realized using four multiplication circuits, one subtraction circuit, and one addition circuit, but in fast Fourier transformers, etc. Since a plurality of complex multipliers as shown in the figure are used, a large number of multiplier circuits are eventually used, increasing the scale and power consumption of the circuit.
この発明は、上記のような従来のものの欠点を
除去するためになされたもので、複素数の乗算を
被乗数、乗数ともに単位演算時間内に時分割配列
して行なうことにより、乗算回路の数を削減して
従来の半分の２つとし、小規模で低消費電力の乗
算装置を提供することを目的としている。 This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and reduces the number of multiplication circuits by performing multiplication of complex numbers by time-divisionally arranging both the multiplicand and the multiplier within a unit calculation time. The number of multiplication devices is reduced to two, which is half that of the conventional one, and the purpose is to provide a small-scale multiplication device with low power consumption.
以下、この発明の一実施例を図について説明す
る。第２図において、１〜６は、第１図と共通部
分であり、２０は被乗数の実数部ａと虚数部ｂと
を単位演算時間内に時分割配列する第１の時分割
回路、２１は乗数の実数部ｃと虚数部ｄとを単位
演算時間内に実数部／虚数部および虚数部／実数
部のそれぞれに時分割配列する第２の時分割回
路、２２と２３は単位演算時間間隔の1/2だけ遅
延する第１および第２の遅延回路、７と８は第１
および第２の乗算回路、１１は減算回路、１２は
加算回路、１３と１４はラツチ回路である。７，
８，１１〜１４は第１図と同じ動作をする回路で
ある。 An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, 1 to 6 are common parts with FIG. 1, 20 is a first time division circuit that time-divisionally arranges the real part a and the imaginary part b of the multiplicand within a unit operation time, and 21 is a 22 and 23 are circuits 22 and 23 which time-divisionally arrange the real part c and imaginary part d of the multiplier into real part/imaginary part and imaginary part/real part, respectively, within unit calculation time; The first and second delay circuits delay by 1/2, 7 and 8 are the first
and a second multiplication circuit, 11 is a subtraction circuit, 12 is an addition circuit, and 13 and 14 are latch circuits. 7,
8, 11 to 14 are circuits that operate in the same way as in FIG.
つぎに、上記構成の動作を第３図のタイミング
チヤートにしたがつて説明する。 Next, the operation of the above configuration will be explained with reference to the timing chart shown in FIG.
入力端子１および２より入力された複素数の被
乗数の実数部ａ（第３図Ａ）と虚数部ｂ（第３図
Ｂ）は、第２図の第１の時分割回路２０で、装置
に備わつているタイミングを用いて単位演算時間
内に時分割配列されて第３図Ｅの出力ａ／ｂを得
る。 The real part a (FIG. 3A) and the imaginary part b (FIG. 3B) of the complex multiplicand inputted from input terminals 1 and 2 are processed by the first time division circuit 20 in FIG. Using the known timing, the signals are time-divisionally arranged within the unit calculation time to obtain the outputs a/b shown in FIG. 3E.
一方、乗数の実数部ｃ（第３図Ｃ）と虚数部ｄ
（第３図Ｄ）は、第２図の第２の時分割回路２１
で装置に備わつているタイミングを用いて単位演
算時間内に時分割配列されて、第３図Ｆに示す実
数部／虚数部に配列された出力ｃ／ｄと、第３図
Ｇに示す虚数部／実数部に配列された出力ｄ／ｃ
とを得る。第１の乗算回路７では、上記出力ａ／
ｂと出力ｃ／ｄとの乗算を行ない、第３図Ｈに示
す積ｅを出力する。第２の乗算回路８では、出力
ａ／ｂと出力ｄ／ｃとの乗算を行ない、第３図Ｉ
に示す積ｆを出力する。 On the other hand, the real part c (Fig. 3 C) and the imaginary part d of the multiplier
(D in FIG. 3) is the second time division circuit 21 in FIG.
The outputs c/d are arranged in a time-division manner within a unit calculation time using the timing provided in the device, and the outputs c/d are arranged in the real part/imaginary part shown in FIG. 3F, and the imaginary number shown in FIG. 3G. Output d/c arranged in part/real part
and get. In the first multiplication circuit 7, the output a/
b is multiplied by the output c/d to output the product e shown in FIG. 3H. The second multiplication circuit 8 multiplies the output a/b and the output d/c, as shown in FIG.
The product f shown in is output.
第１および第２の遅延回路２２，２３では、上
記積ｅ，ｆをそれぞれ単位演算時間間隔の1/2だ
け遅延し（一般的にはラツチ回路が用いられ
る）、第３図ＪとＫに示す出力e1とf1を得る。減
算回路１１では、上記出力e1より積ｅを減じ、第
３図Ｌに示す差ｇを得る。加算回路１２では、出
力f1に積ｆを加え、第３図Ｍに示す和ｈを得る。
ラツチ回路１３と１４では、上記差ｇと和ｈをそ
れぞれ装置に備わつているタイミングを用いて単
位演算時間間隔でラツチして、複素数の積の第３
図Ｎに示す実数部Ａ＝ac−bdと、第３図Ｏに示
す虚数部Ｂ＝ad＋bcとを得る。 The first and second delay circuits 22 and 23 respectively delay the products e and f by 1/2 of the unit calculation time interval (generally, latch circuits are used), and We get the outputs e 1 and f 1 shown. The subtraction circuit 11 subtracts the product e from the output e1 to obtain the difference g shown in FIG. 3L. The adder circuit 12 adds the product f to the output f 1 to obtain the sum h shown in FIG. 3M.
The latch circuits 13 and 14 latch the difference g and the sum h at unit calculation time intervals using the timing provided in the respective devices, and
The real part A=ac-bd shown in FIG. N and the imaginary part B=ad+bc shown in FIG. 3O are obtained.
以上説明したように、この発明では、従来の装
置と比べて乗算回路が４回路から２回路に削減で
き、時分割回路２０，２１、遅延回路２２，２３
の増加分（規模、消費電力ともに小）を考慮して
も、回路の規模、消費電力が削減できる。 As explained above, in the present invention, the number of multiplication circuits can be reduced from four to two compared to the conventional device, and the number of multiplication circuits can be reduced from four to two, and the number of multiplication circuits can be reduced from four to two.
Even when considering the increase in (both scale and power consumption are small), the circuit size and power consumption can be reduced.
なお、上記の実施例では、複素数の乗算が１段
階のみの場合について述べたが、高速フーリエ変
換器のように、複数個の乗算機能をカスケードに
用いる場合においては、各乗算段の出力において
実数部と虚数部の時間配列を次段の乗算段に適す
るようにしておけば、乗算数の時分割回路は初段
に設けるのみで済み、乗算回路の削減効果が一層
大きくなる。 In addition, in the above embodiment, the case where the multiplication of complex numbers is performed in only one stage is described, but when multiple multiplication functions are used in cascade like in a fast Fourier transformer, real numbers are processed at the output of each multiplication stage. If the time arrangement of the part and the imaginary part is made suitable for the next multiplication stage, the time division circuit for the multiplication number only needs to be provided in the first stage, and the effect of reducing the number of multiplication circuits becomes even greater.
以上のように、この発明によれば、複素数の乗
算を、被乗数、乗数の実数部と虚数部をそれぞれ
単位演算時間内に時分割配列して行なうことによ
り、回路規模および消費電力の大きい乗算回路を
削減でき、それだけ回路規模の縮少、消費電力の
低減化が実現できるという効果がある。 As described above, according to the present invention, multiplication of complex numbers is performed by time-divisionally arranging the multiplicand, the real part and the imaginary part of the multiplier, respectively, within a unit calculation time. This has the effect of reducing circuit scale and power consumption accordingly.
第１図は従来の複素数の乗算装置を示す系統
図、第２図はこの発明の一実施例を示す系統図、
第３図は第２図の各部の動作を説明するためのタ
イミングチヤートである。
７……第１の乗算回路、８……第２の乗算回
路、１１……減算回路、１２……加算回路、１
３，１４……ラツチ回路、２０……第１の時分割
回路、２１……第２の時分割回路、２２……第１
の遅延回路、２３……第２の遅延回路、ａ／ｂ…
…第１の分割回路の出力、ｃ／ｄ，ｄ／ｃ……第
２の分割回路の出力、ｅ……第１の乗算回路の出
力、e1……第１の遅延回路の出力、ｆ……第２の
乗算回路の出力、f1……第２の遅延回路の出力、
ｇ……減算回路の出力、ｈ……加算回路の出力。
なお、図中、同一符号は同一または相当部分を示
す。
FIG. 1 is a system diagram showing a conventional complex number multiplication device, and FIG. 2 is a system diagram showing an embodiment of the present invention.
FIG. 3 is a timing chart for explaining the operation of each part in FIG. 2. 7...First multiplication circuit, 8...Second multiplication circuit, 11...Subtraction circuit, 12...Addition circuit, 1
3, 14... Latch circuit, 20... First time division circuit, 21... Second time division circuit, 22... First
delay circuit, 23... second delay circuit, a/b...
...output of the first dividing circuit, c/d, d/c...output of the second dividing circuit, e...output of the first multiplier circuit, e 1 ...output of the first delay circuit, f ...Output of the second multiplier circuit, f 1 ...Output of the second delay circuit,
g...Output of the subtraction circuit, h...Output of the addition circuit.
In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
乗数の実数部と虚数部とを単位演算時間内に時分
割配列して出力する第１の時分割回路と、乗数の
実数部と虚数部とを単位演算時間内に実数部／虚
数部および虚数部／実数部のそれぞれに時分割配
列して出力する第２の時分割回路と、上記第１の
時分割回路の出力と上記第２の時分割回路からの
実数部／虚数部に時分割配列された出力および虚
数部／実数部に時分割配列された出力のそれぞれ
とを乗算する第１および第２の乗算回路と、これ
ら両乗算回路の出力をそれぞれ単位演算時間間隔
の1/2だけ遅延する第１および第２の遅延回路
と、上記第１の遅延回路の出力から上記第１の乗
算回路の出力を減算する減算回路と、上記第２の
乗算回路の出力と第２の遅延回路の出力を加算す
る加算回路と、上記減算回路および加算回路のそ
れぞれの出力を単位演算時間間隔でラツチするラ
ツチ回路とを具備してなる乗算装置。1. A multiplication device that performs multiplication of complex numbers, which comprises a first time division circuit that time-divisionally arranges and outputs the real part and imaginary part of the multiplicand within a unit operation time; a second time division circuit that time-divisionally arranges and outputs the real part/imaginary part and the imaginary part/real part, respectively, within a unit calculation time; and the output of the first time division circuit and the second time division circuit. first and second multiplier circuits for multiplying the real part/imaginary part from the circuit by the time-divisionally arranged output and the imaginary part/real part by the time-divisionally arranged output from the circuit; and outputs of both of the multiplier circuits. a subtraction circuit that subtracts the output of the first multiplication circuit from the output of the first delay circuit; A multiplication device comprising: an adder circuit that adds the output of the multiplier circuit and the output of the second delay circuit; and a latch circuit that latches the respective outputs of the subtracter circuit and the adder circuit at unit operation time intervals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55126798A JPS5752959A (en) | 1980-09-11 | 1980-09-11 | Multiplier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55126798A JPS5752959A (en) | 1980-09-11 | 1980-09-11 | Multiplier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5752959A JPS5752959A (en) | 1982-03-29 |
| JPS6156823B2 true JPS6156823B2 (en) | 1986-12-04 |
Family
ID=14944207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55126798A Granted JPS5752959A (en) | 1980-09-11 | 1980-09-11 | Multiplier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5752959A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0424889Y2 (en) * | 1986-05-30 | 1992-06-12 |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58223846A (en) * | 1982-06-23 | 1983-12-26 | Fujitsu Ltd | Multiplier of complex number |
| JP3759173B2 (en) * | 1997-06-26 | 2006-03-22 | 旭化成株式会社 | Parallel processor and digital signal processor using the same |
| KR100433627B1 (en) * | 2001-12-11 | 2004-05-31 | 한국전자통신연구원 | Low power multiplier for complex numbers |
| JP7317151B2 (en) * | 2020-02-06 | 2023-07-28 | 三菱電機株式会社 | complex multiplication circuit |
-
1980
- 1980-09-11 JP JP55126798A patent/JPS5752959A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0424889Y2 (en) * | 1986-05-30 | 1992-06-12 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5752959A (en) | 1982-03-29 |
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