JPS56168276A - Arithmetic processing unit - Google Patents

Arithmetic processing unit

Info

Publication number
JPS56168276A
JPS56168276A JP7248680A JP7248680A JPS56168276A JP S56168276 A JPS56168276 A JP S56168276A JP 7248680 A JP7248680 A JP 7248680A JP 7248680 A JP7248680 A JP 7248680A JP S56168276 A JPS56168276 A JP S56168276A
Authority
JP
Japan
Prior art keywords
plural
outputs
carry save
multipliers
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7248680A
Other languages
Japanese (ja)
Inventor
Koichiro Omoda
Shigeo Nagashima
Shunichi Torii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7248680A priority Critical patent/JPS56168276A/en
Publication of JPS56168276A publication Critical patent/JPS56168276A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49936—Normalisation mentioned as feature only

Abstract

PURPOSE:To omit a multiplier by making an adder for operating the sum total of plural elements of an array processor usable for the purpose of multiplication. CONSTITUTION:A multiplying means consisting of plural multiple generating means 102-1-102-6 which divide multipliers to plural set and generate the multiples of multiplicands corresponding to the multipliers of the respective sets, carry save adders (CSA) 104-1 and 104-2 which add the outputs from these plural multiple generating means, and an adding means 109 which adds the sum outputs of the carry save adder means and carry outputs is provided, and further a register means which holds plural elements, a digit matching shift means which matches the digits of these plural elements and applies to the same to the above-mentioned carry save adder means, and a means which normalizes the output of the above-mentioned adding means are provided.
JP7248680A 1980-05-30 1980-05-30 Arithmetic processing unit Pending JPS56168276A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7248680A JPS56168276A (en) 1980-05-30 1980-05-30 Arithmetic processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7248680A JPS56168276A (en) 1980-05-30 1980-05-30 Arithmetic processing unit

Publications (1)

Publication Number Publication Date
JPS56168276A true JPS56168276A (en) 1981-12-24

Family

ID=13490695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7248680A Pending JPS56168276A (en) 1980-05-30 1980-05-30 Arithmetic processing unit

Country Status (1)

Country Link
JP (1) JPS56168276A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56147259A (en) * 1980-04-16 1981-11-16 Sanyo Electric Co Ltd Digital signal processing circuit
JPS641060A (en) * 1987-03-04 1989-01-05 Nec Corp Vector arithmetic unit
JPH01230127A (en) * 1987-11-09 1989-09-13 Lsi Logic Corp Digital multiplier circuit and digital multiplier-accumulator circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56147259A (en) * 1980-04-16 1981-11-16 Sanyo Electric Co Ltd Digital signal processing circuit
JPS641060A (en) * 1987-03-04 1989-01-05 Nec Corp Vector arithmetic unit
JPH01230127A (en) * 1987-11-09 1989-09-13 Lsi Logic Corp Digital multiplier circuit and digital multiplier-accumulator circuit

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