JPS56147259A - Digital signal processing circuit - Google Patents

Digital signal processing circuit

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Publication number
JPS56147259A
JPS56147259A JP5081780A JP5081780A JPS56147259A JP S56147259 A JPS56147259 A JP S56147259A JP 5081780 A JP5081780 A JP 5081780A JP 5081780 A JP5081780 A JP 5081780A JP S56147259 A JPS56147259 A JP S56147259A
Authority
JP
Japan
Prior art keywords
switches
multiplication
subtraction
addition
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5081780A
Other languages
Japanese (ja)
Inventor
Takeshi Sakai
Kenichi Murawaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP5081780A priority Critical patent/JPS56147259A/en
Publication of JPS56147259A publication Critical patent/JPS56147259A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce the number of circuit elements to reduce a chip area, by the constitution where a circuit for partial products and a circuit for addition and subtraction of multiplication results are used for multiplication.
CONSTITUTION: In case of sound synthesizing of the linear forecast coding system, (k) and S (or x) are input to multiplier front part 1 in the grid type digital filter circuit under the state where switches 11 and 12 are closed, and the partial product of the maximum order and the sum of partial products of lower orders are obtained, and the former and the latter are input to adder and subtractor 2 through switches 11 and 12 respectively, and the sum of them is obtained as the multiplication result of kS (or Kx) and is latched in 3. Next, switches 13 and 14 are closed, and kS (or kx) and (x) (or S) are given to adder and subtractor 2 through switches 13 and 14 respectively, and x+kS (or S-kx) is obtained as multiplication and addition and subtraction results by addition (or subtraction) in 2.
COPYRIGHT: (C)1981,JPO&Japio
JP5081780A 1980-04-16 1980-04-16 Digital signal processing circuit Pending JPS56147259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5081780A JPS56147259A (en) 1980-04-16 1980-04-16 Digital signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5081780A JPS56147259A (en) 1980-04-16 1980-04-16 Digital signal processing circuit

Publications (1)

Publication Number Publication Date
JPS56147259A true JPS56147259A (en) 1981-11-16

Family

ID=12869308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5081780A Pending JPS56147259A (en) 1980-04-16 1980-04-16 Digital signal processing circuit

Country Status (1)

Country Link
JP (1) JPS56147259A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127039A (en) * 1976-04-16 1977-10-25 Hitachi Ltd Control system for multiplication and division
JPS56168276A (en) * 1980-05-30 1981-12-24 Hitachi Ltd Arithmetic processing unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127039A (en) * 1976-04-16 1977-10-25 Hitachi Ltd Control system for multiplication and division
JPS56168276A (en) * 1980-05-30 1981-12-24 Hitachi Ltd Arithmetic processing unit

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