JPS57178544A - Multiplication system - Google Patents

Multiplication system

Info

Publication number
JPS57178544A
JPS57178544A JP6500481A JP6500481A JPS57178544A JP S57178544 A JPS57178544 A JP S57178544A JP 6500481 A JP6500481 A JP 6500481A JP 6500481 A JP6500481 A JP 6500481A JP S57178544 A JPS57178544 A JP S57178544A
Authority
JP
Japan
Prior art keywords
register
product
partial
multiplier
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6500481A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6500481A priority Critical patent/JPS57178544A/en
Publication of JPS57178544A publication Critical patent/JPS57178544A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even

Abstract

PURPOSE:To improve an arithmetic speed greatly without providing special hardware by multiplying a multiplicand by two firstly, finding the sum of said result and partial products stored in an answer area, and thus finding the partial products. CONSTITUTION:When it is judged that a multiplier is >=2, a selector 14 outputs some value, preset in a double-product register 13, selectively. An operating device 15 adds said value set in the double-product register 13 to a partial product stored in an answer area. Simultaneously, the operating device 15 performs subtraction ''multiplier-2'' for next arithmetic. The sum of the double product and partial product is shifted to right by some digits through the shifting function of the operating device 15. Its output is held as a partial product in a partial product register 16. Thus, one cycle ends and next constant-digit data set in a multiplier register 11 is checked similarly, thus obtaining a multiplication result by a register 16.
JP6500481A 1981-04-28 1981-04-28 Multiplication system Pending JPS57178544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6500481A JPS57178544A (en) 1981-04-28 1981-04-28 Multiplication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6500481A JPS57178544A (en) 1981-04-28 1981-04-28 Multiplication system

Publications (1)

Publication Number Publication Date
JPS57178544A true JPS57178544A (en) 1982-11-02

Family

ID=13274411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6500481A Pending JPS57178544A (en) 1981-04-28 1981-04-28 Multiplication system

Country Status (1)

Country Link
JP (1) JPS57178544A (en)

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