JPS5759245A - Double-length multiplier - Google Patents

Double-length multiplier

Info

Publication number
JPS5759245A
JPS5759245A JP55133794A JP13379480A JPS5759245A JP S5759245 A JPS5759245 A JP S5759245A JP 55133794 A JP55133794 A JP 55133794A JP 13379480 A JP13379480 A JP 13379480A JP S5759245 A JPS5759245 A JP S5759245A
Authority
JP
Japan
Prior art keywords
multiplier
double
multiplication
fixed bit
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55133794A
Other languages
Japanese (ja)
Inventor
Toshi Ikezawa
Hirohisa Karibe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55133794A priority Critical patent/JPS5759245A/en
Publication of JPS5759245A publication Critical patent/JPS5759245A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To achieve the multiplication of double-length bits through using one multiplier of fixed bit length, by dividing the respective digits of multiplier and mulitplicand into 1/2, by finding their partical product three times, and by multiplying it. CONSTITUTION:A prescribed multiplier A and a prescribed multiplicand B are divided into the upper priority digit and lower priority digits, namely, AM and A1, plus BM and BL respectively, and they are stored in registers 1-4. Through selectors5 and 6, the AM and BM, AM and BL, plus AL and BM are inputted selectively to a multiplier 7 of fixed bit length, where a partial product 1 CMM=AMXBM, a partial product 2 CML=AMXBL, and a partial product 3 CLM=ALXBM are obtained. Then, said partial products 1-3 are accumulated to obtained a multiplication result C=CMM+CML+CLM. Consequently, the multiplier 7 having fixed bit length achieves the multiplication of double-length bits, so that the multiplication of double- length bits, even if required occasionally, is carried out by one inexpensive mulitplier with fixed bit length.
JP55133794A 1980-09-26 1980-09-26 Double-length multiplier Pending JPS5759245A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55133794A JPS5759245A (en) 1980-09-26 1980-09-26 Double-length multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55133794A JPS5759245A (en) 1980-09-26 1980-09-26 Double-length multiplier

Publications (1)

Publication Number Publication Date
JPS5759245A true JPS5759245A (en) 1982-04-09

Family

ID=15113169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55133794A Pending JPS5759245A (en) 1980-09-26 1980-09-26 Double-length multiplier

Country Status (1)

Country Link
JP (1) JPS5759245A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083140A (en) * 1983-10-14 1985-05-11 Hitachi Ltd Multiplication system
EP0161089A2 (en) * 1984-04-26 1985-11-13 Nec Corporation Double precision multiplier
JPS6184736A (en) * 1984-08-14 1986-04-30 テ　アール　テ　テレコミュニカシオン　ラジオエレクトリック　エ　テレホニク Processor for data processing in various modes
JPS62145468A (en) * 1985-12-20 1987-06-29 Oki Electric Ind Co Ltd Processor for processing signal
US4754421A (en) * 1985-09-06 1988-06-28 Texas Instruments Incorporated Multiple precision multiplication device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083140A (en) * 1983-10-14 1985-05-11 Hitachi Ltd Multiplication system
EP0161089A2 (en) * 1984-04-26 1985-11-13 Nec Corporation Double precision multiplier
EP0161089B1 (en) * 1984-04-26 1992-04-29 Nec Corporation Double precision multiplier
JPS6184736A (en) * 1984-08-14 1986-04-30 テ　アール　テ　テレコミュニカシオン　ラジオエレクトリック　エ　テレホニク Processor for data processing in various modes
US4754421A (en) * 1985-09-06 1988-06-28 Texas Instruments Incorporated Multiple precision multiplication device
JPS62145468A (en) * 1985-12-20 1987-06-29 Oki Electric Ind Co Ltd Processor for processing signal

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