FR2320602A1 - Sequential binary number multiplier - has simultaneous controlled shift registers containing parts of multiplicand and assodicated with adder and AND:gates - Google Patents

Sequential binary number multiplier - has simultaneous controlled shift registers containing parts of multiplicand and assodicated with adder and AND:gates

Info

Publication number
FR2320602A1
FR2320602A1 FR7524256A FR7524256A FR2320602A1 FR 2320602 A1 FR2320602 A1 FR 2320602A1 FR 7524256 A FR7524256 A FR 7524256A FR 7524256 A FR7524256 A FR 7524256A FR 2320602 A1 FR2320602 A1 FR 2320602A1
Authority
FR
France
Prior art keywords
adder
gates
shift registers
assodicated
multiplicand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7524256A
Other languages
French (fr)
Other versions
FR2320602B1 (en
Inventor
Jean-Pierre Houdard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA filed Critical Alcatel CIT SA
Priority to FR7524256A priority Critical patent/FR2320602A1/en
Publication of FR2320602A1 publication Critical patent/FR2320602A1/en
Application granted granted Critical
Publication of FR2320602B1 publication Critical patent/FR2320602B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product

Abstract

The sequential binary multiplier multiplies a p-bit number B by an n-bit number A. M simultaneously controlled shift registers second the multiplier divided into m words A1-Am. Each word is formed by the bits of A with weights increasing in an arithmetic progression of ratio m. The first bits are made up of the weight bits O to m-1 of A. The multiplier has m stages of addition and multiplication associated with the m registers, each having P 'AND' gates and an adder. An accumulator output register of p-bit capacity receives the binary word delivered at the p outputs of the adder of the last stage and transmits this word to the adder of the first stage.
FR7524256A 1975-08-04 1975-08-04 Sequential binary number multiplier - has simultaneous controlled shift registers containing parts of multiplicand and assodicated with adder and AND:gates Granted FR2320602A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7524256A FR2320602A1 (en) 1975-08-04 1975-08-04 Sequential binary number multiplier - has simultaneous controlled shift registers containing parts of multiplicand and assodicated with adder and AND:gates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7524256A FR2320602A1 (en) 1975-08-04 1975-08-04 Sequential binary number multiplier - has simultaneous controlled shift registers containing parts of multiplicand and assodicated with adder and AND:gates

Publications (2)

Publication Number Publication Date
FR2320602A1 true FR2320602A1 (en) 1977-03-04
FR2320602B1 FR2320602B1 (en) 1979-03-30

Family

ID=9158721

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7524256A Granted FR2320602A1 (en) 1975-08-04 1975-08-04 Sequential binary number multiplier - has simultaneous controlled shift registers containing parts of multiplicand and assodicated with adder and AND:gates

Country Status (1)

Country Link
FR (1) FR2320602A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0186864A1 (en) * 1984-12-27 1986-07-09 Siemens Aktiengesellschaft Fast digital multiplier
EP0188779A1 (en) * 1984-12-27 1986-07-30 Siemens Aktiengesellschaft Fast digital multiplier

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1086043A (en) * 1953-07-02 1955-02-09 Electronique & Automatisme Sa Improvements to multipliers for digital electric calculators
GB796404A (en) * 1953-08-27 1958-06-11 Nat Res Dev Improvements in or relating to electronic digital computing machines
FR2148871A5 (en) * 1971-08-06 1973-03-23 Cit Alcatel

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1086043A (en) * 1953-07-02 1955-02-09 Electronique & Automatisme Sa Improvements to multipliers for digital electric calculators
GB796404A (en) * 1953-08-27 1958-06-11 Nat Res Dev Improvements in or relating to electronic digital computing machines
FR2148871A5 (en) * 1971-08-06 1973-03-23 Cit Alcatel

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0186864A1 (en) * 1984-12-27 1986-07-09 Siemens Aktiengesellschaft Fast digital multiplier
EP0188779A1 (en) * 1984-12-27 1986-07-30 Siemens Aktiengesellschaft Fast digital multiplier

Also Published As

Publication number Publication date
FR2320602B1 (en) 1979-03-30

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Legal Events

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