SU385272A1 - DEVICE FOR STRIPPING - Google Patents

Description

one

Device Applies to aiBTOMaTHiKe and computing. I

A device is known for multiplying the numbers containing (Multiplier multipliers and multipliers connected through the partial product formation scheme, the pyramid of adders and the circumferential transfer scheme to the output buses of the device. In this device, the partial products are generated simultaneously and added to the adder, but this time depends on the number of partial works, which reduces speed.

The proposed multiplication device is different in that it additionally introduces partial decryption schemes and sequential folding up to two numbers of rows of the multi-part code of the terms, the number of which series is equal to the binary logarithm from the number of terms at the input of this scheme. The outputs of each stage of the decryption and coagulation scheme are connected to the inputs of decoding and coagulation of the next stage, and the outputs of the last stage of the schemes of decryption and folding through the end-to-end transfer scheme with the output tires of the device. This allows you to podvysit device performance.

Pa figs. 1 shows a block diagram of the proposed device; in fig. 2 - block diagram

adder of partial products for five terms; in fig. 3 - a single bit decoder circuit is functional for four inputs.

The device (see Fig. 1) contains the / r-bit multiplicative register /, the t-bit register of multiplier 2, connected through the circuit 3 of formation of partial products. The outputs of the formers of partial products 4i-4t of the circuit 3 are connected to the inputs of the adder 5, and the outputs of the generator of partial products 4 are connected to the inputs of the bit decoders from the 1st to the t-th discharge, the outputs of the generator of the C to the inputs of the decoders from 2- Go to (t + 1) -th bit, etc., and the output of the former 4, n - with the inputs of the decoders from the n-th to (2m-G) discharge. The outputs of the adder of the partial products 5 are connected to the output tires of the device.

The adder of partial products 5 (see Fig. 2) contains decoders of products — schemes for decoding partial works and sequential folding 6. The outputs of 6-degree zero-level decoders are connected to the inputs of decoders of the first condensation 6, the outputs of which through first-transfer circuits 7 are connected with output tires device. The numbers on the outputs of the decoders indicate the number of units on their

output.x at which a unit appears at a given output. For example, if 5 units are supplied to the decoder 6 ° 5, then there are only one unit of hardware in the first l of the fourth output of the decoder.

Partial decoders produced neither 6 (see Fng. 3) contain coincidence circuits 8. Busbars of primary products (4P) and their inversions (4 | P) are connected. To the inputs of coincidence circuits 8, the outputs of which are combined, and form the output decoder tires.

Device; works as follows.

In order to multiply the two / i.rai numbers, one number is taken for the register of the multiplier. /, The other for the multiplier 2. Of these registers is used for the partial education scheme, 3 for x products, from which all In the forward and inverse codes, the products are fed to a partial 1P1rO1is | veDe) H1H1Y 5 adder, where the linear is entered into one-time, one-dimensional, and all of them are fixed; x works and 1YVs | 1Pros1 programs;

The simultaneous summation of the next slice on the sum of partial production is summed up in the stepwise formation of hyphenations from the / -th bit into several higher ranks so that

1 aj

V2p;, / d.

  about

where Р j (i is the transfer from the i-th bit of the t-th step to (l + q) -K bit of the (t4-l) -OH step. At the same time, the total is produced by those q that participate in Transfers. For example, measures, dl. and K 10. and SSU Iog2 1., g and 3 participate in the Transfers, since.

Thus, in this case, transfers will be made from the / -th bit of the g-th step to the (/ + 3) -th bit and (/ + 1) -th bit of the (/ + 1) -th step. The stepwise formation of carries ends in the last stage, which is similar to the zero & stage of a conventional adder.

Gain 1. Multiply the multiplicand 11111 by the multiplier 11-101 (with the last step of the decimal, the ripening is the first step).

. Multiplication table number 1

Continued table. umghozh No

10 Note. The index above the number in the table indicates the number of the bit in the given stage, for which the transfer unit into this unit and the bit is assigned.

Check:

Mill

X

MliOl L 1 / M 00000

11111

MiliLl L 111

1 MOOOQOl 1

Ex. 2. Reduce the multiplier 10101 a. Multiplier 11 M 1.

Multiplication table number 2

Number of units at the entrance of the discharge

Check:

10101

X

11111 10101 10101 10101 1010 10Ю1

10100010 M

Subject and s about b ip e t € -n. And

A device for multiplying, containing registers of the minimal multiplier, connected through the formation scheme of partial production, the pyramid of su.mators and the end-to-end transfer scheme with output devices, characterized in that, p. the purpose of gaining momentum of the device, in it additionally | & there are schemes for decrypting partial productions and sequentially folding up to two the number of rows of the multiscale addendum code, the number of rows of which is equal to d; the military log of the number of addends circuits, with the outputs of each steps

385272

The decryption and coagulation schemes are connected to the inputs cxeiM of the next stage, and the outputs of the last stage of the decryption and coagulation schemes through the end-to-end transfer scheme are connected to the output shims of the device.

Wj y / 7j W Wj W5 Ws Y / 7g Wj Wj Y / 7, W W 5 W, W W, V / 7,

| 5-l stage

1st stage of state of emergency Shch fn ChP W W2 W, V / 7j,

FIG. 2

W, V / 7y