JPH0295440U - - Google Patents
Info
- Publication number
- JPH0295440U JPH0295440U JP425489U JP425489U JPH0295440U JP H0295440 U JPH0295440 U JP H0295440U JP 425489 U JP425489 U JP 425489U JP 425489 U JP425489 U JP 425489U JP H0295440 U JPH0295440 U JP H0295440U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- carry
- outputs
- result
- arithmetic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は、この考案の一実施例を示す構成図、
第２図は、記憶装置に記憶されるデータを示す図
、第３図は、この考案の他の例を示す構成図であ
り、図において１は演算器、２は記憶装置、ａ及
びｂは入力される２進数、ｃは桁上げ信号または
桁下げ信号、ｄは演算結果、ｅは出力信号である
。なお、図中同一符号は同一または相当部分を示
す。
FIG. 1 is a configuration diagram showing an embodiment of this invention.
FIG. 2 is a diagram showing data stored in a storage device, and FIG. 3 is a configuration diagram showing another example of this invention. In the figure, 1 is an arithmetic unit, 2 is a storage device, and a and b are The input binary number, c is a carry signal or a carry down signal, d is a calculation result, and e is an output signal. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
し、ある一定値以上、またはある一定値以下の値
が出力されるのを防止する装置において、２つの
入力端にそれぞれ入力された前記２種類の２進数
の演算を行い、第１の出力端に演算結果による桁
上げ信号または、桁下げ信号を出力し、第２の出
力端に演算結果を出力する演算器と、上記演算器
から出力される桁上げ信号または桁下げ信号と、
演算結果とを入力し、入力信号に従い記憶したデ
ータを出力する記憶装置とで構成したことを特徴
とするリミツタ装置。 In a device that prevents a value greater than or equal to a certain value from being output as a result of calculating two types of given binary numbers, the two types inputted to two input terminals respectively. an arithmetic unit that performs arithmetic operations on binary numbers, outputs a carry signal or a carry down signal according to the arithmetic result to a first output terminal, and outputs the arithmetic result to a second output terminal; a carry signal or a carry down signal,
1. A limiter device comprising: a storage device which inputs calculation results and outputs stored data according to an input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP425489U JPH0295440U (en) | 1989-01-18 | 1989-01-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP425489U JPH0295440U (en) | 1989-01-18 | 1989-01-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0295440U true JPH0295440U (en) | 1990-07-30 |
Family
ID=31206605
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP425489U Pending JPH0295440U (en) | 1989-01-18 | 1989-01-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0295440U (en) |
-
1989
- 1989-01-18 JP JP425489U patent/JPH0295440U/ja active Pending
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