JPS5821299A - Reverberation sound adding apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION ζO is a me sound adding device KIIL, which has a long distance and an irregular amplitude level. The IIg# sound and the regular 1* resonant sound are synthesized and applied to the 11A installation with the reverberant sound that is generated.

Conventionally, as a device that produces sound through a single electronic path, there is the llID (Ba5k@tlIriga4).
・D・My・・）中CCD（Ckarg＠C＠mpl
・dD・Mal@I) using DoO analog Haruko Nobuko If vhemo0#many is ζO, the oI circuit configuration is the 11th
As shown in a typical OK-to example, it has an fIk quantity loop FIL that feeds back its own delayed signal output to the input side, and a signal obtained by adding the input musical tone signal and the feedback signal is passed through a delay circuit DCK consisting of 11110 etc. to pDT. There is one that outputs time-varying grinding.

According to the configuration 〇-ro like Jin, as shown in Figure 3,
Reverberant sound exhibiting a regular impulse response determined by the delay time of the delay circuit DC and the feedback loop FILO gain f is obtained.

When we analyze the reverberant sound that occurs at the end of a hall, etc., we find that it reflects from the floor in one wall and has a large amplitude level and delay time, as shown in the impulse response characteristic aK in Figure 3. The irregular early reflected sound MCH is first heard as Kij4, and then a reverberant front wing V with regular amplitude level and reverberation time appears. Therefore, tlI
With a configuration like the one shown in Figure i1, it is impossible to generate the natural reverberant sound that can be obtained with a Nnert Hall system.
K.

Sototo, as shown in the 4th garden, the delay time is ZUNDAM KW
k fixed animal multiple O cyclic ■ connection DO > ~ DO, series KII
After this, the delay signal level of each delay abrasive circuit DCt to DCmOII is controlled independently by the slow abrasive control circuits GCI to GC*, and these are combined in a composite circuit CC to obtain the impulse response characteristics shown in Fig. 3. There are nine types of early reflected sound eCH and reverberant sound RV that can be generated.

However, in order to generate natural-looking reverberation with the configuration shown in Figure 4, K requires the installation of a large number of delay circuits, which increases the scale of the equipment and makes it less economical. There are 6 and 9 flaws.

Jin's invention overcomes the above-mentioned drawbacks of the conventional reverberation sound adding device, and its purpose is to create a small-scale and economical structure that is natural! To provide a reverberation sound adding equipment capable of generating IIIp sound.

Therefore, the reverberation sound adding device according to the present invention has a device that generates reverberation sound with irregular delay times and levels, and a feedback loop for outputting delayed signals, and generates reverberation sounds with regular delay times and levels. It is possible to generate natural reverberation sound by combining it with a device that produces natural reverberation.

Hereinafter, Jin's invention will be explained in detail based on examples.

Fig. S is a four-dimensional diagram showing one embodiment of the reverberation sound adding device by Jin's threat, Fig. 6 is a functional block diagram functionally expressing the configuration of the embodiment, Fig. 7 and Fig. 5sii. This is a block diagram showing the basic configuration of the ninth delay circuit that uses digital memory to generate reverberation sound with a desired zero delay time.

＠＠＠＠＠＠＠＠＠2t First, we will explain the basic configuration and operation of the delay circuit shown in Figures 7 and 8, and then explain the formation of reverberant sound from the function of the 6th cabinet. Next, the specific structure and operation of the II pongee example shown in the illumination will be explained.

Basic configuration of nine delay circuits using digital signals Amplitude data 11PD(t) of input musical tone signals obtained by sequentially amplifying digital signals at a predetermined sampling period T.
If the data is stored sequentially as time passes, the large amplitude data IPD (t-1) is stored at time (1-1,).
To read out at the 9th time number after 1 hour has passed, the address information tsum DR(t)K when the sampling time is t is changed to the address interval tsum DR that changes at the time of 1 hour to the next +11th
As shown in equation (2), the addition process is completed, the address information ADR(t-1) at time (t-1)K is obtained, and this address information DIE(t-1) is obtained. All you have to do is give the address of the digital memory manually.

AD Tsubasa (s-1) M D turtle t) + no ADR...
...+1) Mu DB (t-1) = Mu D true t) - Tsumu DR
・・・・・・・・・ (2) As a result, time (t-
1) In the memory field, store the amplitude data 5pD (-fish) as 1 Δm DRXT...
...This can be solved by reading out with a delay of one hour as shown in (3).

That is, the address interval Δ corresponding to the desired delay time 1
If ADR is given as delay time information, time (i-1)
The large amplitude data 8PD(t-1) can be stored with a delay of i time and read out. In this case, address information MDR(t-
1) is the amplitude data 8PD (applied when the illusion is stored sequentially from a high address to a low address as time passes). (t) is stored sequentially from a low address to a high address.

Therefore, the delay circuit in Jin's death uses the amplitude data gp
yt), and a digital memory DM for sequentially storing yt), and a readout ydv shown in equation (1) or equation (2) above.
Basically, an address information generation circuit G that forms the xffl information DIE(t-1) and a delay length data memory DDM that generates the address interval DI as delay time information DLD are provided.

FIG. 7 is a block diagram showing an example of a delay circuit based on this concept, which includes a digital memory DM, an address information generation circuit G, and a delay length data memory D.
It is equipped with a DK and a multiplier M.

The digital camera DM converts the clock pulse φKm (amplitude data 5pzt) which is numbered at a predetermined period i.
O For each address, from the high address "9" to the low address r
configured.

Amplitude data 8PD (
The designation of the phantom write address and read address is performed by the address axis generation circuit G. That is, the address information generating circuit G includes an address column C and an adder D, and the write address information circuit D and D are updated as the sampling time is updated.
(t+1), Mu Da(t+2).

...-ADR(t-H) and the read address information MDR(t-H) expressed by the above-mentioned silent) formula.
1) and outputs it as address information DM/mu DR of the digital memory DM. That is, the address column C counts clock pulses φ with a period To, and converts the count value into amplitude data 5PD (phantom write address information ADR() at the current sampling time tK).
t), and adder D
K supply. On the other hand, delay length data memory DD
M is time information DLD()A corresponding to the desired delay time IK
DiLzl/T@) is supplied to the adder module DO and other adder power. Then, at the numbering time t, the adder D first performs the calculation expressed by the above-mentioned equation (1), and uses the calculated value as the amplitude data IIPD(t-1) of one hour before.
The translated address information notification wing (t-1) is output, and then the output information (Dot) of the address column C is outputted as it is as the amplitude data aPD(t)0 at the current time tK of tiJA.
It is output as write address information (D■t).

As a result, at time t, the amplitude data IIPD (t-1) of one hour ago (stored at t-0) is read out from the digital memory DM, and the amplitude data 11 F at the current time t is read out from the digital memory DM. D(t) is stored at the address specified by the address format D group t).

In this way, the amplitude data 5pa(t-i) is read out from the digital memory DM with a delay of one hour, and the amplitude data is 11MK.
Th is multiplied by a coefficient K for amplitude level control to perform level control. Then, the level-controlled amplitude data
11PD(t-1) is converted into an analog signal by a digital converter MIK (not shown). In this way, the tkWIJ operation is performed every sampling W# time.

As a result, it is possible to generate a sound of 1141, which is 91 hours different from the input electric sound. In the case of sound, if a plurality of different O delay time information DLDs are sequentially provided in one sampling time in a time-sharing manner, information regarding a plurality of reverberant sounds having different viewing times can be extracted within the same sampler time. Therefore, in this example of a theory of failure, the delay circuit shown in FIG. Complex 1k1 where the delay time varies randomly during the amplitude level depending on the distance to the reflector such as the IO wall
It is used to form early reflections with acoustic characteristics.

FIG. 8 is a block diagram showing another example of the delay circuit,
In the delay circuit of this example, the address column C of the address information generation circuit q is constituted by a down counter of a preset lid. Then, by presetting the grinding time information DLD corresponding to the desired delay time lK for the address counter ACK and performing a down-count operation from this value (DLD), p1 is output from the address counter JAC. Address information MDR(s), ADR(t+1
) ,...ADR(t+1)0 repetition period is specified by delay time information DLDK), KL is set to match the delay time, and amplitude data 5pD at current time Bc (
The amplitude data 8PD(t-1) stored one hour ago is read from the address where t) is to be stored.

If you replace it, the digital DM will be like the 8th HO <10
When configured with Akebono, the maximum value of the address interval is ``10''.
'', it is possible to read 8 PD (t-10) of time-varying nine-convergence data with a maximum of 10-'1',
When the desired O delay time amount is, for example, 6·TI, the address counter ACO output information DM·ADi! wo5.4.3
．． 2.1.0.5. - Repeat the song 00, reduce the @ range of the address used in the digital memory DM corresponding to the desired delay time (Kami6・T・)K, and set the current time t.
Make sure that the address to which sampled amplitude data gPD(t) is written matches the address to which the amplitude data &FD(t-1) just one hour ago was written. Amplitude data written 1 hour ago from the address where data & FD(t) should be written! I
There is a 40″1? that reads PD(t-1).In the ninth row of this sea, the output information DM/MUDR of the address column C changes from “0” to “ 9
A maximum value detection circuit MXD is provided which detects when the delay length data memory DDM changes to 9 and uses this detection signal to pre-init the time information DLD output from the delay length data memory DDM to an address counter CK.

On the other hand, the 8th IiIC)liIiiwA road C sampled at 11mt and obtained nine amplitude data 5pD(
t) is not written to the 11th digital memory DMK, 1
The amplitude data 8PD(t-1) from the previous time is fed back at a predetermined rate, and the sum of the feedback value; 5pD(t-t) and the amplitude data 8PD(t) sampled at the current time t is written. It is designed with K to make it more immersive. For this,
A multiplier M multiplies the amplitude data 8PD(t-1) of one hour ago read from the digital memory DM by the K coefficient K and sends #ljl to the data input side of the digital peak DM, and the output data of the multiplier M 11PD(t-1) and the amplitude data 5pD(t) at the current time t, and the added value "
An adder D is provided for supplying 8PD(t)t- and -8FD(t-1)J to the data input of the digital camera DM.

Therefore, in the nine-delay circuit configured in this manner, when the desired delay time i is 6T, the address column CK is set so that the output information DM and the output information DB of the column C are r.
When the maximum value (rOJ in this example) changes from OJ to the 9th point in time, delay time information (DLI) expressed as DLD-8-1-1$ is preset. As a result, the address counter AC changes as the sampling time O progresses (sampling period T/every K)!
I, 4.3.2.1.0. ! S, . . . repeatedly outputs address information DM/MUD that changes to -0. At each sampling time, the amplitude data from one hour ago stored at the address specified by the address information DM-ADII! IPD(t-
1) is read out at t, and then the amplitude data Hatake PD(t-1
) and the amplitude data l1PD sampled at the current time t.
(t) and 9 data rspn←)
+K·5pD(t-1)J is written.

Therefore, in the delay circuit configured in this way, the current

Amplitude data 8PD at the current sampling time tKjiP
(1) Write address and amplitude data one hour ago IPD
Rounding where the reading address of (t-1) is the same and the amplitude data 5pD (t-t) of one hour ago is fed back,
It is difficult to extract data regarding reverberant sound whose amplitude level and duration vary regularly. Follow? In the embodiment of the present invention, the delay circuit shown in FIG. 8 is used to generate a regular 41% reverberant sound after the initial reflected sound is generated.

In addition, as the amplitude data 8PDK coefficient K is multiplied, the level of the amplitude data 8PD of the source of the data regarding the reverberant sound finally obtained increases and overlaps, so the data regarding this reverberant sound is not included in *@. The reverberant sound is guided to the output section through an attenuator.

In this case, if the coefficient K is set to r-1(K(OJ), no attenuator is required.

Next, using the functional block diagram shown in FIG. I will clarify.

The formation and exit of the reverberant sound in the example of Yokoji in Figure 6 is I
I@Shizurushi and the process of forming an early reflection sound whose delay time changes randomly, and this early reflection sound! ! The process of forming reverberant sound in which the amplitude level and delay a time regularly change.

Here, these early reflected sounds and reverberant sounds are formed independently of each other by a series of nine delay circuits.

At step 6111, the input musical tone signal is encoded at a predetermined period and nine amplitude data gPD(t) is supplied to the early reflection sound forming section 1, which is the first delay circuit series.

The early reflected sound forming section 1 uses nine delay circuits as shown in FIG. At the current sampling time m*, read out the message Do having the memory address 04g@0 and the message DObh at the current sampling time.
@am l~10) Previous 10 types of amplitude data jlPD
(t-1t), arp(t-1s)s **+am+
Multiplication @Ml-M that multiplies 8PD (t-1n) by an arbitrary amplitude level control coefficient KB (+agsu~10)
IG and the multiplication value output of these multipliers IIO.
IIPD(t-1s), K-Rose・5pD(t-1s)s
・・・・・・K1・・8PD(t−1t・) total D(
t-In) is the instantaneous value E of the early reflected sound at the current time t.
It consists of an adder SUN that outputs as CM (CM).

In addition, addition @BUM is the total sum of the above +1) Built-in register RO for temporary storage at t.

In the early reflected sound forming section I having such a configuration, amplitude data 8! of the input musical tone sampled at the current time t is generated. '
D(t) is written to the running address corresponding to the current time t among the 2048H storage addresses of the memory DO. Next, the register 80 in the adder SUM contains the sum at the previous sampling time (t-1)K, "1", and the contents of this register RO are reset to the primary order, 1m
10 types of amplitude data before time 5pa (t-ss) ~
At the ninth point in reading out amplitude data 11FD (t-1t) of delay time 11 out of 1gFD (t-11.) from memory DO, the address of memory DO corresponding to delay time 11 is specified.

The nine-body width data Hatake PD (t-11) is sampled 11 hours ago from this address. In this case, the address for reading the 11-hour-old own width data 5pD (t-it) is determined by the above-mentioned (1).

In this way, nine delay times 1i0 amplitude data/I
PD(th-h) is input to the multiplier MIK and the multiplier M
In l, delay time 110 pieces 1 reflected sound men.

The coefficient for amplitude level control corresponding to is multiplied by 1.

Then, the 1,000 OSS value and JiPD(t-11) are inputted to the adder 8υMK and added to the current value of the register RO42), and the added value is stored again in the register ROK.

In this case, the contents of the register RO are rounded which are reset to the right edge of the current time 10 amplitude data IIPD(t)0 writing, and the contents written to the register ROK at this time are the data I
Kg・gpD(t-1t).

' In this way, the amplitude data IPD with a delay time of 11
(t-1*) () Bladder discharge m and level control #! & When the task is completed, that is, when the processing related to the tuna 1 reflected sound ICHt is completed, then the delay time 1mo 2nd reflected sound tuna CH
Amplitude data 11FD (t-1m) in sK tone 0 reading processing and level control processing are performed in the same manner as the formation processing of the first reflected sound ICHI. As a result, an addition of 111U
The register RO in M contains t related to the 1st reflection sound cH1.
f −/IC1・8PD(t−1t) Second reflected sound 1cH To the data regarding snow, add 0・8PD(t−1,) and 0 addition value rKs −5PD(t−1t)+ic,−5p
D(t-ts)J is stored.

Processing like Jin is 3rd reflection sound Tobi CHI ~ 10th reflection sound I
The same applies to CIII@. As a result, the register 凰 OK is from the 1st reflected sound ICH* to the 10th reflected sound 1I.
CHnK#Sui amplitude data pK, ・l1pp(t-i
1) -x, pot - is #I1 reflected sound EC1h ~ $10
Instantaneous value of reflected sound ECHsa or humming early reflected sound 1cII
(t) is output via the switch In.
.

The switch circuit 1W sets the initial reflection sound formation processing time Ta within the sampling synchronization T as shown in the following table 111.
In , the output of the register RO is selected and outputted, and at time Tb, which is the first initial reflection sound formation processing time, the output of the second delay circuit series is selected and outputted.

Information selectively output by the switch circuit SW in the first table
eI[t) is converted into an analog signal Km by a Dm converter (not shown), and is applied to a rear speaker, where it is produced as an initial syllable for the input musical tone.

Therefore, 1st reflected sound ICHI ~ Hall 10 reflected sound ICH>・
By varying the O delay time 1 m and the amplitude level control coefficient Ill, it is possible to obtain early reflected sounds whose amplitude levels and delay times vary randomly, as shown in FIG.

Here, set the sampling synchronization To of the input musical tone to 0.04m.
g (if 25KH), the amplitude data at the current time t8
For example, when reading the amplitude data gpn (t-1626) stored at the address 16261i away from the write address A D R (t) of PD(t), the delay time i is 65m in 1-1626X0.04. - Tonashi, input musical tone) Early reflection sound EC delayed by about 65m5
M, can be generated.

On the other hand, amplitude data 5PD(t)Fi obtained by sampling the input musical tone at a predetermined period i.sub.4 is supplied to a second delay circuit series that forms reverberant sound after the initial reflected sound is generated.

This second delay circuit series has amplitude data IIPD(t)
a delay memory DIO that delays by one hour and supplies the band pass filter 11PFK; and a low pass filter that passes only a predetermined frequency band component of the amplitude data 8PD (t-j) with a delay time j supplied from the DIO. LP
The reverberation sound data RVD with a coarse delay time interval is formed based on large amplitude data 1mFD(t-J)K after passing through a digital bandpass filter BPF consisting of a F filter and a bypass filter HPF, and a wrinkled bandpass filter IFF. Consisting of a first reverberant sound forming unit 2 having a 111m1 filter configuration, and a second reverberant sound forming unit 3 having an all-pass filter configuration that forms reverberant sound data RVD with a self-propagation time interval based on the reverberant sound data RVD. has been done.

In such a configuration, the large amplitude data IPD(t) sampled at the current time t is 2
048 Among the memory addresses of Akebono, nine addresses corresponding to the current time t are written. Next, the message DI
Read out the data gPD(t-J) of one hour ago among the large amplitude data gPD(t) stored OK.The address of the memory 010 corresponding to the rounding and delay time jK is specified, and the address of the memory 010 corresponding to the delay time j hours is specified, and Kt sampling large amplitude data II
PD(t-J) is read. In this case, the address for expressing the JIS Sekimae amplitude data 5pD(i-j) is 9th (1), as in the case of early reflection sound formation.
Required by Ni. The delay time j at ζ is set to be slightly thicker (j>ss*) than the -delay time h* for the 10th reflected sound ICCHI*.

The delay time j read out from the memory DIG in this way
The amplitude data 8PD (t-J) is the low-pass filter LP.
It is input to the multiplier Mll of F, and is multiplied by a predetermined coefficient [11 in ζζ. Then, the multiplication value [11・5
pD(t-j) is temporarily stored in register RIK.

Next, 1 from the memory 8DO having the storage address of 1@
The large amplitude data 5pD (t-j-1) written before the sampling time (1・T・) is read out, and the data of 8PD is read out.
(t-j-1) 11 is multiplier MI to the constant coefficient of KFji
Multiplied in I. Next, add 1ra PD (t-J -1) and register xJfl to the multiplier value output of 1 multiplier M120.
K temporarily stored O amplitude data j hours ago Kll・5
pD(i-J) is added and the added value [K11・8
PD(t-J-1)+Kal・5pD(t-J)J is temporarily stored in register RIK again and is stored in register 12.
Next, the amplitude data 5pD written one sampling time (1・T・) before the current time t.
(t-J-1) is read out again from the message gDO, this data 5pD(*-J-1) is multiplied by a predetermined coefficient K1m in the multiplication IIM13, and this multiplication value L
s-11FD (t-J-1) is register R1! The value temporarily stored in “Klm・5pD(−j−1)+l[
olPD(t-J) is added to J, and its addition value section xllPD(t J 1) + Kt plate・8PD
At (t-J)+, 1r gpD(t-J-1) is temporarily stored again in register B'lK. Next, in order to use the value “Klm・IIPD(−J−1)+Kst・IPD(t−J)J” temporarily stored in the register blade IK in the next sampling period (t+1), this value rKs
1x 5pD (t-j)J to rlPD(t-j-1)+
is written to memory 1iDoK.

If such an operation is performed in each sampling period Tt41, the output of the bus filter LPF will be
jl:6-6FiFjr1ii? lt area〒Roma 17 to 1
Further, the amplitude data 8PD(t-j) of one hour ago is output, and the amplitude data SDE(t-j) of the last hour is sent to the bypass filter HPFK.

Then, in the bypass filter HPF, the amplitude data gpn(i
-J. ), low frequency components in a predetermined band are removed.

ffkb'b, register 11 of low-pass filter LPF
The second output data gPD(t-j) is input to the multiplier M14, and is multiplied by a predetermined coefficient K14 in the second multiplier M14. Then, the multiplication value is 8PD(t-J)
is temporarily stored in register R3. Amplitude data aPD (t-
j-1) is read out, and this data 8PD(t-j-1)
It is multiplied by K predetermined coefficients KlB in multiplier M15.

Next, the multiplication value obtained from the multiplier M15 is
(t-j-1) is 1 temporarily stored in register R3.
14・1iPD(t−j) is added to the amplitude data before the time, and the added value [K・8PD(t−j)+K
xa-8PD (t-j-1)'' is temporarily stored in the register 13 and also temporarily stored in the register R4.

Next, the current time tyopl・! sampling time (1・T・
) The previously written data 5pD(t-J-1) is read out again from the memory SDI, and the ζO readout data IPD(t
-j-1) K is multiplied by a predetermined coefficient In in a multiplier Ml@. Then, this multiplication value 1[xs4PD(t-J
-1) is temporarily stored in the register wing 4, and the value rKs
a・BPD(*j)+Kti4PD(t-J-1)J
1...8 PD (t-J-
1) + K mouth・gpp(t-j)+Ks easy・8PD(
t-J-1) is temporarily stored in register 凰4. Next, the values rKsa and IIPD(t-j) temporarily stored in the Lujista blade 3
+Lr1lPDCt j-1)J is used in the next sampling period (t+1), this value "K14・gPD
(tJ)+Ksrll'D(tJ 1)J is written to memory 8DIK.

Due to the fact that such an operation is performed every sampling period T, the regime of the bypass filter HPF is
From this, low frequency components in a predetermined band are removed and amplitude data 5pa(t-j) of one hour ago is output.

Note that the low-pass filter LPFO register 81 is not used in the next oty pulling cycle t after the contents of the register are written to the message 8DO, so the bypass filter HP
It can be shared with FID register R3.

In this way, the amplitude data 8pn(t
-j) is input to the first reverberant sound forming section 2.

The first residual tone forming section 2 includes three delay circuits 2A, 2B, and 2C arranged in parallel, each having a comb-type filter configuration having different delay times. 3 delay circuits 2A, 21°20
are provided in parallel when the frequency characteristics of the delay circuit with the IIWiy filter configuration are independent.
This is to flatten the waveforms shown at B and C at step 1540. In other words, 3 different delay times
By providing the delay circuits 2A and 2C in parallel, it is possible to flatten the oys divisor % as shown by the symbol in FIG. 11 as p11. In this case, the degree of flattening improves as the number of parallel connections of delay circuits increases.

In this embodiment, the delay time of the two delay circuits is up to 4 times longer,
Next, the delay time of the delay circuit 2m is set to be the longest, and the delay time of the delay circuit 2C is set to be the shortest.

Each of the delay circuits 2A, 2B, and 2C has the same configuration, except for the delay time setting.

Therefore, in the figure, only the numbers of the multipliers, registers, and memories are shown for the circuits 2B and 2CK, and only the delay circuits 2B and 2CK are shown.

In the first reverberation sound forming section 2 having such a configuration, the amplitude data 8 of five hours ago that has passed through the band pass filter BPr is
PD(t-J)K is obtained by first inputting a coefficient x1y for amplitude level control in the multiplier M17, and then temporarily storing the multiplier value xty·gpn(t-J) in the register R5 in the multiplier M17. be remembered. Next, read out the amplitude data 8FD (tll) written 11 hours ago in the memory D1 having the storage address of 204gAkebono, the slow grinding time xl
The address of the memo DI corresponding to lc is specified. Therefore, the amplitude data II of 11 hours ago is stored in the memory D1.
PD(t-xs) is read out. Then, this amplitude data 8PD (t-=odds) is supplied to an adder 5UNK, which is then sent to other memories D2 and D30 output data and delay circuits 2B and 2CO memories D4 to D6.
．． It is added with the output data of D7 to D9, and the adder SUM
It is temporarily stored in register R11 within. In this case, the read operation of the memories D1 to D9 is carried out in time division among the memories D1 to D9, and when the read operation of the memory DI is performed, data is output from the other memories D2 to D9. Not yet. The contents of this rounding and writing to the register 811 in the adder 80M become data gpn(t xl) read from the memory Dl.

On the other hand, amplitude data 8P4 n read from memory D1
(t
It will be R. And co multiplication value Lr8PD(t-xl)
is the data stored in register R5 at the current time t, !・5pD(t-J) is added, and the added value is 17・8PD(t j)+Kts・8PD(t-XI
) is temporarily stored in register R6. Next, register R
The amplitude data stored in 6 “K11・8PD(t-j)
1l-11FD (t-x 1 ) J is written to the same address as the x1 time-0 amplitude data gpn(t-xs) stored therein. Ovk, the contents of register R6 are reset. Read the contents of register R6.

The purpose of sorting is to transfer this register R6 to memory D in the next step.
It is good that it can also be used as part 11 of the 24D system.

When the processing of the memory Di system is completed in this way,
Next, processing is carried out in the same manner as in the processing furnace of the memory D2 system.

That is, memo D with address 204g Akebono
Amplitude data 8PD written 2fCxH time ago (t1
3) Memory D2 corresponding to the ninth point to read out the variable resistance time xzK
0 address will be registered. As a result, the amplitude data IPD sampled X1 hours ago from the viewing page D2 is read out. Then, this amplitude data gPD
(t-x snow) is register 111 in addition 118UM
0 contents (9 contents read from memory D1) apn(tl
t) and addition 1tL, its added value 11PD(t-xm)
+1iFD (g11) J is temporarily stored in register R11.

On the other hand, nine amplitude data aPD(t
ll) is multiplied by a coefficient x1 for amplitude level control in the multiplication @wxe, and then fed back to the input side of the memory D2. Then, the multiplied value is 1−・JiPD(t−xm
)' is the value Kxy・g temporarily stored in register R5
PD(t-J) and the added value “K11・5p
D(*-J)+Kts-8PD(t-x snow)J is temporarily stored in register R6. Nine data rKxt・aPD (t-j)+Ls −8PD are written in this register R6.
(t-xm) J is data from X1 hours ago! IPD(t-
x) is stored at the same address where it was stored. After this, the contents of register R6 are set.

Next, the process for the memo 983 is performed in the same way as the process for the memo IJD2.

Therefore, at the stage when processing of the memo IJDI to D3 series is completed, if the delay time of the memory D3 series is xs, then
The contents stored in register R11 are 8PD (t-<t
)+8PD(t-is)+lil'D(tlg), and the contents Ksy -5pD stored in memory 03
(t-J)+l(ms・8PD(t-xs).

Such processing is similarly performed in delay circuits 2B and 2C.

Therefore, memory D4. D5゜Di
The delay time of each I/O system is set to X4. X ink, X
I, Oh Kuharu I! Memari D7. D.I.
.

The total time of each DIO is set to x4. XI, X
For reference, the contents of register R11 at the 9th stage after all 4DMII of delay circuits 2m to 2C are completed are m Ji
PD(t-xx)+8FD(t-is)+JiPD(t
-Xs)+8PD (t-14)+Jip6 (t-x
s)+IFD(t-xs)+8FD(t-xy)+11
As a result, following the early reflection sound, the delay time interval is coarse as shown in No. 1211, and the amplitude level and delay time change regularly. This produces a reverberant sound. In addition,
In FIG. 12, the reverberation sound is shown only for the ninth delay circuit 2' where the time relationship is complicated.

The coarse reverberation sound data RVD formed as described above with a large delay time interval O is input to the second reverberation sound forming section 3.

The second residual sound forming section 3 is provided with delay circuits 3A, SB, and 3C in series that are composed of all-pass lid filters with flat frequency characteristics.

The reason why the three delay circuits 3A, 3B, and 3C are provided in series is because the reverberation sound data RVD with a closer delay time interval than the reverberation sound data RVD obtained in the first reverberation sound forming section 2
This is to form a Therefore, the delay time of each delay circuit SA, SB, SC in this second reverberant sound forming section 3 is equal to the delay time of each delay circuit 2A, 2 in the first reverberant sound forming section 2.
B, the delay time of 2C) is set 4 shorter. Each of the delay circuits 3A, 3m1, and 3C has the same configuration except for the delay time O setting. Therefore, in the figure, delay circuit 3B.

Regarding SCK, only the numbers of multipliers, registers, and memories are shown, and the detailed configuration of only the delay circuit 3 is shown.

First, the reverberant sound data RVD output from the second reverberant sound forming section 2 is supplied to the register 111K of the delay circuit 3, but 512% of the data RVD is stored in the register R12. A message M with a memory address of
To read data from DOKF written 1 hour ago (t-yx), even if the address of the memory MDO corresponding to the delay time of 11 hours is specified, this will cause the data to be written from the MDO to be written yi before the delay time. The weighted data RVD' (t-7x) is continuously output. Next, in multiplication 5M30, the coefficient for amplitude level control is multiplied by 1, and the multiplication value IC1@, RVD" (t-yt)
411 Mn0O is fed back to the input signal. Then, this feedback data Ks...the data RVD which is also supplied from the wing VD (i-tx) and the first reverberation sound forming section 2 at the current time tK.
(t) is added, and the added value rBVD''(t
)+Ks* ・RVD” (t-Fl)J HaV
') Temporarily stored in Star 12. Next, the delay time is 1M.
The memory MDOt) address corresponding to is specified again,
Written 11 hours ago from Memine 9MDO ★re9 data A■ (
t-yx)-IIX is released one after another, and the seven revealing data R
VD ''(t-yt) is temporarily stored in the register blade 15K.Next, it is temporarily stored in the register blade 1, and the 9 data rRVD''(t)+1Cse-RVD'(t-1
s) J and the amplitude "CJ4z control O constant Kse is multiplied in the multiplier M29.Then, the multiplied value Kn-(RVD"(t)+Kse・RVD'(t-
FB)) is added to the value 1mVD'' (-11) temporarily stored in the register 1131, and the added value RVD' (t-71) +Ku ・(RVD''(t
)+Ks*-RVD" (t-yl)) is temporarily stored in the raster R13. Next, the data rRVD(t)+Ks@・RV temporarily stored in the register 112
DI(t-yl)J is rounded to be used at 9 numbering times (t+yx) after yt time from current time t.
t F 1 ) J Fa Time ago data RVD” (
t-71) is stored and written to the same address as the 19th address.゛When the processing by the delay circuit 3 is completed in this way,
Regimeta IIIK Stored data RVD' (t-
y, )+IC5s・(avn”(t)+−・・Ayu F
D''(t-yρ) is sent on the delay path SIK, and this onaa
In the road s1, the same process as in the 1st road 3m O field is performed.

In this ζ, the delay circuit 3m, 1m, 3CO output data IV
D", RVD", IVD"t' Table h) L, 1 path sm If the delay time between OII resistors is ys*@path 3C delay time ys, circuit 3m, $1, 3C registers R13, R1
The output data of 5,117 is represented by the following Oth (4) 2 to (6) 2.

RVD"mu wealth IVD' (t-ys)+l[u-(
RVD”(t)+l[ie 0RVD”(t-Fs))
"-...="14IVDs-11VD"mu(
t Fg )+Ks1 ・(RVD"'(t)+Ks
s・RVD"mu (t-FM)) --------
・-・------(53RVD"-ciLVD"(Hs
) +Kss ・(RVD”(t)+Ks+・IVD
” (t-ys)) ”=”== (6)
Then, the output data 1lVD'' of the delay circuit 3CO is outputted via the switch circuit IIW as rounded data that generates reverberant sound following the initial reflected sound.

Here, each far-sighted circuit Sm)l, $CO extension delay, 11
When it is set to Σy*)ysO■, it is possible to form a delay time interval of 0 tklllI as shown in the stripe diagram 13.

In other words, the delay number 3 is the 111th sound formation part! Formed with 1 delay time interval O @ based on reverberant sound data 1VDl, the delay time interval of the 11111th sound form is p4 smoke time interval 1 time #E10! The delay circuit 3m generates the reverberation sound data RVD"l of the tuna 3 at a time interval 1M which is 4 Km longer than the circuit 3m-delay time interval 11.
form. Therefore, as the reverberation sound formation process S in the visual circuit 3~8CK progresses, the delay time interval 01!
One stone so that F & reverberation sound is formed.

Note that the delay circuit $A, S1. Register R1 in SCK
! ! , Rb, since the wing 16 is not used until the next sampling period after its own circuit Kll error has finished,
They meet by sharing time-sharing.

Next, the specific configuration and operation of the fifth embodiment shown in IIIK will be explained. In the following explanation, it will be assumed that the apparatus shown in FIG. 5 forms reverberation sound in accordance with the functions described above and shown in FIG. 6.

Specific configuration of the embodiment II shown in No. 511! The reverberation sound adding device of Koji Example can be roughly divided into storage section 16. Time information school club 20. It is composed of an address information generating section sO9 arithmetic section 40.

The storage unit 10 is the digital memory DMKI@ for viewing in the 811th storage unit, and is composed of a data card 100 and a ratte 101 having a number of values in the ζζ wall. In the data measurement 100, by using a plurality of O memory blocks, 111 (H! bit) O memory 1100-alD15 as shown in No. 14-
And 51! all (16 bits per day)
) Q-MDIS, and 204811 (1111 is 16 bits) methods JIIDO to D1z are provided. And, Tonome 49100~gD15. MDO~MD15゜D
The data to be stored is also given to the arithmetic unit 40, and the storage address and display address of the data are output from the address information storage unit SO, so the address information DM.
If you are a designated store by DIK, please contact IDO~D1s.
The data read from the arithmetic unit 4 through the latch 11
It is configured to be supplied to the

The time information generating section 20 (shown in FIG. 8) includes a parameter specifying circuit 200 and a delay length data memory 201. In accordance with the instructions from the parameter designation circuit 2011, memory DO~
DI! ! , MDO~MDIII at, 1ait time information DLD" (m) (m: DO~DIS, MDO-
MD 15 Cal 49 ill, m: 1-808
1) is configured to selectively output one of the types. That is, the delay length data memory 201, as shown in FIG.

~MDI! ! Corresponding to each of them is Nine Memory Lip Yotsuta Ml (
DO) ~ Ml (DiS), Ml (MDO)
~Ml ([91B), each memory block M
ll(DQ) to Ml(MDIS) are respectively described above.
Seed @1) *8 memory addresses rOJ~ corresponding to the tatami amount
It has "7" and 1 month-w 7'ay/Ml (DO) ~
MB (MDIS) 0 Each memory address “0” to “7” has different watch time information DLD” (Do) to DLD
"(Do), DLD" (DI) ~ DLD torture (Di),
---DLD” (Dll) ~DLD Lu (Dll), D
LDI (MDO) ~ I) LD I (MDO) , --
-----DLD 1 (MD 1s) ~ nx# (MD
15) is stored in advance. And then, a pet generated! Parameter instruction information @PIIL consisting of 3 bits that instructs the reverberation characteristics of reverberant sound is supplied from the parameter instruction circuit 200 as lower address information, and further processed by MDO to MD.
15. Do ~DISe message number information DLm of 4-bit configuration that specifies the message conversion number "O~■1" (So: O~1
! $ ) Mail type information DLk (k: JM
D-8D) is supplied as upper address information from the address information generation section, information DL.

and DI, the message block (Mll(
DO) 〜Ml(MD15)1iD out of 1),
Storage address specified by information pgL (“O” to “7”)
one of them)K stored delay time information DLD'[
m] is successively outputted and supplied to the address information generating unit -sO as information defining the one-striking time relationship of the reverberant sound of the desired OII reverberation specified in the parameter specification circuit 200. In addition, memory 100-101! ! Since the 13-time extension time is fixed (1-T), this memory 8D
Since the delay time information is not required for O to BDISK, the parameter designation circuit 200 uses the parameter designation information P8L and the desired control program to form the 8 types @O reverberation sound. Program selection information PG8 consisting of 3 bits for selecting one program 0 is output.

Next, the address information generation section 30 generates the time information generation section 20.
A rounding function that forms reverberant sound with desired O reverberation characteristics based on the delay time information DIJ)" (*) output from It generates address information DM and MUDR for the data memory 100, and also generates various control signals for controlling the operation of each circuit.
2. Control signal output register SOS, *rector 304. Address counter 305, latch 306. subtraction circuit soy
, maximum value detection garden path 30$, address information output circuit 3'I
and i.

The Prodaramme Kagomori 300 has 8 types of reverberation characteristics OII.
Eight types of control programs are pre-stored in the sound-acoustic volume generator jP6. Which type of control program should be outputted is determined by the program selection information PG from the parameter designation circuit 200! Specified by I.

Then, the specified nine control program contents are master data ■
Tsukupal: Puwara Gram Cow that counts X-ga 71$0
10 output information PCK is sequentially read out for each step.

In this case, the early reflected sound forming section 1, which can be explained in Section 6III,
All processes of the bandpass filter IIPF, the first reverberant sound forming section 2, and the second reverberating sound forming section s are performed at one sampling period (
% def 19f 1 frequency to end within T.)!
5111. The master clock is pulsed, and the contents of this 192-step control program are repeated every 9y, every cycle T.Kl! will be carried out. The control program for each step is as shown in Table 2.
Type 1 consists of 6 bits of information. Type 2. Type 3
03 types of contents are prepared and the formation of early reflection sounds.

Filter processing and reverberation sound formation are performed by combining the output order of these three types of control programs and the content of each bit information.

Table 2 In this case, the one-step control program consisting of 1@bit is
(In), the control signal is output via the control signal output register 3OS, and the memory write control signal is output as a control signal (after being decoded by the program decode memory 302, the control signal is output via the PSOS). There are many outputs, and the latter has an operating code O.
4 files can be found in the computer programmer's manual v302 from sOO, which is used as a PC. In addition, Table 2 OP
When I talked about the details, he interrupted me by explaining how the metal body worked.

On the other hand, as shown in the address counter sosFiwni diagram, the delay memories DO~DIS, MDO~MDIR(t
Address columnant C (Do) corresponding to each J
AC (015), AC (MDO) ~ AC (MDI! 111.t"t", this address counter 5osi
c'sP each color I AC(DO)~AC<D
i5) *AC(MDO)~AC(MDlB
) service, memory number information DLm and memory type information DL
k Selectively activated by K. The information DLm and DLR make it operational and the address x* w)
(11:Do~D15.MDO Kashi DI)
! S) t) It counter output information (m) is supplied to the address information output path sO- via the latch 30 and is also supplied to the subtraction circuit 301. In this case, address counter AC(m) 0 output information DR(m) is memory Do-DIs, MDO-MDI! ! Since D()-Dis has an address length of 2048 Akebono, it is configured with Kll bits so that 2048111 can specify the O address range. In addition, the address counter 30s is composed of a.
1”, and the subtracted value [muDR(n]-1J is the next t
After the pump switching period (t+1), the signal is returned to the input signal of the Tata 384 for use. At the same time, it is supplied to the maximum value detection circuit 301. 8th mO in maximum value detection circuit $08
Detection path] ffDK equivalent, address number information DL* and memory type information DLklC, specify address Qa) D output information DIl (
Destroy [1] from [II] and obtain information rADIl(m)-1J
When it detects that K difference is the maximum value (all bits are "1"), it outputs a control signal gLl that causes the selector 304 to select the 1 input. The selector 304KTh selects the subtraction circuit 3070 output information “MUDR(
a) −1J is input, delay length data memory 2010 output information DLD” axis is input to the input,
Its output is supplied to the address counter 5osoy-p input to write the write control signal W for the address column C61) specified by the information DL@*DLkK.
ISk is configured to be written (preset). Therefore, information DL grave.

Address counter specified by DLkK (AcD&)K
Then, under the condition that the maximum value detection circuit SOS is not generated and the control signal IILI is not generated, "1" is removed from the current value MDR4 [-] at the first printer opening period 41, and the nine value "MUDI" is removed. (m)-1J can be written [1, soO
The output information value D[1] decreases in the rOJO direction as time passes. However, when the value "MUDR(!1)-IJ" reaches the maximum value, the selector control signal iiL is generated from the maximum value detection circuit 3o$, so the address column (2) is delayed via the selector 304. Time information DLD
”(a) is input, and the write control signal WB, 3 causes the write operation. Therefore, 1 of the address counters AC61)
1 is selected by generating the select control signal ILIO.
(n) After becoming accustomed to J, as the sampling time passes, K
It changes sequentially in the direction of rOJ. That is,
Seletaku 304. Address counter SOS, latch 3H
.

In the part consisting of the subtraction circuit 3.T and the maximum value detection circuit 3o8, the delay time information DI, I) (m
) An address information group Di(m) is formed that goes around at a period equal to the K correspondence S i (m).

The address information DR(m) is supplied to the address information output circuit 10-.

The address information output circuit sO- is the memory lID0-ID
IIS, Me4SDo-Dis, Me'Ssi[)0~M
Information O read and write round address information for D15 is output. When the address information output circuit 3-- reads out the 111 time nine information from the me49DO and forms the initial reflected sound I Cn(t), the address information output circuit 3.
The 11-bit address information Or.mu DRn (output from the control signal output register SO3) corresponding to each travel time 11 is used as the lower address information, and the memory number information DLn and memory type are placed above it. Add information DLk, ζ01! The IO information OF-me DRm, DLm, and DLk are output as address information DM-ADR. ν, when sampling at the current time and writing nine amplitude data gpD(t) to the memory DOK, the output information DR(DO) of the address counter AC(DO) corresponding to the memory DOK is taken as the lower address information, and the memory is written to the upper one. Information specifying page 00 DLm (company Dl, .) and DLk (-DLD)
Add , Jin's set of information AD wing (DO), DLm
, DLk as address information DM/MUDI.

E9. When writing and reading amplitude data to and from memory ID0 to 8015, set all bits of the lower address information to @O" and write a message to the upper part of the bit.9 BDO to 8
Specify D15 Information DLn (wDL*~DLII)
and DLk (mD and ■) and address information 11DM
・Output as mu DR. Goose, reverberant front wing VDI, RV
When forming D', MJIvDt-D15, M
DO~MD15 Corresponds to vtree-1' f4 address column C(DI)~AC(Dlg), AC(MDO)
to AC (ID15) 04 output 111aoi (Dx) ~
ADI (DI5), Mu DR (lωO) Hemu Di (ID1
5) is the lower address information, and the information DL is above it.
m and DLk, and these one set of information m DR(n
), DLm, and DLk are output as address information DM/mu DI. In this case, when the information Or.mu.DRm is to be added to the lower order of the information DLm and DI, a control pulse GPI is output from the control signal output register SO3.

E9: When all bits of the lower address information added to the lower order of the information DLm and DLkO have reached 10''k, the control pulse GP2 is output from the control signal output registers 3.3.

Note that the address information output circuit 30m is internally provided with a register for temporarily storing information @DLm and DLk.

Next, the calculation unit 4 operates on the memories DO~Dig, MDO~M
DIIS, ID0-11DIsK Data to be stored and data to be read from each main peak %O to perform amplitude level control, coefficient value 400. Selector 401. Arithmetic ■ Bribe 402. Tempo tree register 403. A latch 404 is provided.

Like the delay length data memory, the coefficient memory 400 has eight memory blocks corresponding to eight types of reverberant sounds with different reverberation characteristics, and each type of on-reverberation volume is formed in each block. A set of coefficients Kn(n
:i to 32) are stored in advance. Then, the parameter specification path 200 to I (the parameter specification information PliL is supplied, and the address information DR (
Km) is supplied from the control signal output register 30m, information A of the program that can be specified in the information PAL is
DR(Km) "t'il coefficient I from the specified address
The configuration is such that n is read out and supplied to the calculation input (A)K of the calculation circuit 402.

Selector 4@la, sample and hold circuit 8
Pl [Kyo] Sampled 9 input sound collection OII width data 8! 'D(t) is input and B11 manually stores memory section 1.
If the read data MRD is input from the input register 4D8t), the output data ROD is input to the input register 4D8t) through the latch 404.
#PD(t), MRD, RGD are select control signals BL1 output from control signal output registers 3 and 3.
(2-bit configuration) Either one is selected by K, and the arithmetic circuit 4.! The calculation human power is supplied OK.

In the arithmetic circuits 4-2, the arithmetic input (2) is read from the coefficient memory 400, the round coefficient is inputted, and the output data IGD of the tempo register 403 is inputted via the arithmetic operation input (-)Klatte 4-4. Selected output data (ilP output), MRD, RGD) of the dragon I4H is input to the calculation input), and the calculation control signal cwt (3-bit configuration) is output from the control signal output register 10s. (b) Fable (2)
)・■10(2) ・・・・・・・・・(7-1)(
b) to M-)+-) ・・・・・・−・(7-
2) (a) to steal) ・・・・・・・・・
(7-3) (a) Dew (to) ・・・・・・
...(γ-4) (a) Proverb e) ...
・・・・・・(7-1) Execute O operation and calculate the operation value (
b) in Tenbora 9 register 408. The memory section 1 is configured to supply 100K of output registers.

Tempo tree register 4118ti, early reflection sound] cC true.

Reverberation sound RVD, RVD O formation exceeded 11Kjl! The operation am4020tlE calculation value (a) is temporarily stored, and the stored contents are set as register output data RGD by the selector 401.
o, C input and arithmetic circuit 4GHD arithmetic input oI
)K feedback is good, and register designation of i-bit configuration ff
@RGm(!l:1~32)K] Specified 3! It has registers IBO to R31, and input data is specified by the information wing G and written into the large register (RO-131) K under the control of the write control signal Wife.

Next, the output register SOO is the instantaneous value ECM(t
) and the instantaneous value 1vn(t) of the reverberation sound following the early reflection sound
is deceived by the write control signal wag, and this acquired data is attenuated by the DM converter (DAC) through the IlI501.
Supply glue 02.

1k or select control signal 11 in selector 401
LI and calculation control signal CTL in calculation circuit 401
This includes an operating code opcK output from the control signal output register sOs.

Next, the operation of one or more configurations H')h is 1M! I will clarify.

Operation*1jl a, Formation operation of early reflected sound When forming early reflected sound mcm(t), (11 First,
Current time t″etet sampling force musical tone O amplitude data a
To write PD(t) to memory DOK, gLl;8M
The select control signal BL1 and the arithmetic control signal CTL having the contents indicated by LBCT (transfer) CTLi and the operation control signal CTL are outputted from the control signal output register 3o3 in response to the operation code OPC. As a result, the selector 401 transfers the amplitude data 8PD(t) outputted from the sampling hold path mPH to the arithmetic circuit 402.
Supply to 0 operation input ■. The calculation circuit 402 receives the calculation input QQK and outputs the amplitude data 11PD (9) as a calculation value (a).

(Next, in order to write the output data s p n (t) of the arithmetic circuit 4 and 2 to this address, specify the address of the 9 4 s DO corresponding to the current Ot non-pulling time (t)K, DI shift; DL・DLk g DLD !14 Book@1" (wRITl) L3 蓚@1" (LATCH) Memory type information DLk, write control signal WR4, 9R4 side control signal 1.II is operating As the code OPC, the 9th memory number information DL is output from the control signal output register 30s.

As a result, the output information DR(DO) of the address counter C(DQ) corresponding to the memory DoK is latched into the lattice 30@ as the rounded lower address information for writing the current time 10 amplitude data 5pD(t). It will be done. Then, the address information output circuit 301 outputs the latched lower address information DL(Do) to the upper digits of the address information output circuit 301.
(-DI, D) is added and the write address information of the amplitude data 8PD(t) for the peak Do is
Output as 8. As a result, the current time toai width data 8PD(t), which is given to the data input in the memory Do via the arithmetic circuit 402, is transferred to the write control signal WR.
4 to write to the address corresponding to the current time tK.

(8) Next, rounding and wing Gm to clear the register RO that stores the initial reflection sound value for each sampling time.
i 10 C'l"L ; 10 Wikl g "1"(Wll'rl) indicates the arithmetic control signal CTL and write control signal Wll as the operating code OPC, and the overlay register number information IG- It is output from the control signal output register 3@s.

Therefore, rOJ is written to register 8OK, so
That is, the register Re is cleared.

(4) Next, the OF which forms the first reflected sound NCHs
・ADlm; OP・Mu Dlt DLk G DLD GPI i @1"Lm;@1"(LA'rcH) indicates the message type information DLk, control pulse xopi, ttsufflAm1l1 L2 is the operation tampering code OPC
Therefore, nine address information OF.mu.Din is outputted from the control signal output register 303 corresponding to the first reflected sound NCHsO travel time 1sK. In this case, the address information output circuit 301 holds the memory number information DLm (-DL.) in step (3)k.

As a result, the address information output circuit 5osa, the address information otom Dis corresponding to the uniform polishing time 1rK are set as lower address information, the memory number information DLm (婁DL・) and the memory type information DLk (-DLD) are set as upper address information, Amplitude data 8 written 11 hours ago from memo 9DO
Address information DM-A for reading PD (t-1s)
Output as DR. This is k], 11 from memory DO
The amplitude data IPD (t-11) of Ichimaso is successively outputted, and the read data 8PD (t-11)//Ii latch control signal is latched into the latch 11.

(61 Next, the current value of register 11G is latched 404
The latch control signal L1 with the content indicated by Gm1RO Ll i "1" (LATCII) is transferred to the operating code,
Overlapping register number information set is control signal output register 80
Output can be increased from s. This allows the register to of
The A current value is transferred to latch 4o4 and stored therein.

(6) Next, the amplitude data 71lPD (t-H
) is multiplied by IIk@level control 01Al[*, and the first
The instantaneous value of the reflected sound is 1 gPD (t-1t
), rounding to obtain Ml)R(Km); MDB(Kl) gLl; IIILIcTII)CTL
The output control signal 5L1 and the calculation control signal CiL shown by i■・■10-)=(A) are used as the operating code OPC and as the address information module D for reading constants.
R (Km) is output from the control signal output register 30s. As a result, the first reflected sound XC is output from the coefficient memo +740.
1 is successively outputted to the coefficient corresponding to the H value and supplied to the calculation input member of the calculation circuit 402. In addition, the selector 401 selects the amplitude data gPD (t-11) of 11 hours ago since it has been supplied from the ratte 101 to the selected data I
IPD (t-1t) is the calculation input QOK of the calculation circuit 402.
The arithmetic circuit 402 is supplied as follows:
)・(3)+Qi)−Kt・8PD(t−10+(R
The operation indicated by O) is performed. In this case, the contents of the register are the rounding cleared in step (3) above, here the instantaneous value of the III reflection 18catKIl 't ·I! 1PD (t-11) is the arithmetic circuit 402
It is obtained as the calculated value (a).゛(7) Next, add 1 gPD to the instantaneous value of the first reflected sound ICHsO.
(t-11) to be stored in the register RO, the write control signal WRI (indicated by RG*1; RO WRI i "1" (WRITE)) is used as the operating code OPC and the register number. Information RGm
is output from the control signal output register sO3.

As a result, 1.8 PD (t-11) is written to the output data (7) of the arithmetic circuit 402 in the register ROK.

ζ Finish the step in this step)
oK is the first reflected sound 1ccHto instantaneous value Kt-11PD (
- Kame 0 is obtained.

(On the gradient, 3rd reflected sound 10Hm - iris 10th reflected sound 10HI
・The instantaneous value 'D(t-11)～group ・
・8PD (self-11・) is both speed O step (4) to (7
) can be formed in the same way. *The 10th Anti-Dark Blue LC
After completing the step mO operation regarding group C, at the ninth stage,
Write control signal w for register 1G register i@@
It is written by itHc and transferred to attenuator lHK.

b. Filter operation When performing a filter operation...Os, memo') A large one-hour amplitude data layer tD (*-j) from DIG, DLmiDLOtori, DLk i DL.

L3; @1'(LATCH)'L2; R1
” (LATCH) The content indicated by O memory type information DLk, the latte control signal L3.
Output from the OS.

Therefore, the output information DR (DIG) of the ninth address counter C (DIO) corresponding to the memory DIOK is latched to the latch 30 as the ninth lower address information from which the amplitude data 'BpD<t-J) of one hour ago is read. @ is latte.

Then, Jin's latched circle lower address information M D8 (D
IG) is added with memory number information DLm (aDLl) and memory type information DLk (=DLD) above it in the address information output circuit 309, and has an amplitude f-7gFD for the data memory 1060)+1JD1OK.
(tj) is output as the starting address information DM/mu Di. Accordingly, j hours wII are elapsed from the memory DIG.
The line width data IPD(t-j) of the line width data IPD(t-j) is output from the bladder, and this bladder output data IIPD(t-J) is the latch control signal L! The signal is latched by the latch 101.

(2) Next, at the current time t, t sampling is performed.
To write #FD(t) to the same address xlc as the mi@day/IIPD(t-j)0 address, #L1 襥111LIcTJ C? Internal O select control signals SX, XsP and calculation control signal CTLllll & operator Vmln code OP indicated by L i (r) 聰■
The control signal is output from the control signal output register SOS as C.

As a result, the amplitude data IPD(t) output from the 4@lat sampling hold ■path aPH is calculated and the calculation input (X)K is supplied. nine,
The arithmetic circuit 4 outputs the large oscillation data IIPD(t) inputted by the arithmetic operator as a calculated value.

(3) Next, write one-width data IPD (t) to 7%9D10, rounding, DLm g DLt・DLk $DLD WB2; The contents O memory type information DLk, the write control signal W14, and the control signal LN are output as the operation code OPC, and the control signal DLm is output from the digital camera 30s.

As a result, the ninth address counter/AC (DIO) 0 output information MDR (DIQI) corresponding to the memory DIOK is latched into the latch 30@ as the ninth lower address information in which the current time 10 amplitude data 5pD(t) is written. .and,
This latched lower address information module (01G)a
, in the address information output circuit 8@I, memory number information DLm (DLII) and memory type information @DLk (=DLD) are added to the upper part of the address information output circuit 8@I. The write address information is output as DM/mu Di. With this, the operation −
The amplitude data IPD(t) at the current time t, which is input to the memory DIGO data manually via the path 402, is written to the nine address corresponding to the current time tK by the write control signal WR4K.

(4) Next, in the low-pass filter LPF, the inner coefficient of the register 11 is set to ■, and the J time line width data 11PD
(t-j)K), (R1)+1C11・gPD(t-J), rounding to store this calculated value as register number information, first, RG Karasu;lI Lm;"1"' (LA The latch control signal L1 indicated by 'l'CII)O contents is
Also, the register number information RGm is output from the control signal output register $03, and the contents of the register F1 are transferred to the latch 404.

(51 Next, perform the calculation of K@@・!IPD(t-j), MuD wing [Kzen]; MuD wing (L t ) fl
lrLl g IICLIC? (11) CTL
tel)-" Contents indicated by #OQ+(11) O- contains the left control signal ILI, the arithmetic control signal CAL as the operation code OPC, and the O address information ADR (In) for reading the meeting constant from the control signal output register sO3. As a result, the coefficient gtt is outputted from the coefficient memo: S-OO and supplied to the arithmetic operation circuit 402. Latch 1@IK Selects the latched amplitude data 8PD (t-j) and applies it to the arithmetic circuit 40.
20 calculations human power aOK supplied. By this, the calculation times j
! 402a, (a)=A-(a)+-) The following calculation is performed. In this case, the contents of the register 110 are cleared at the stage where the filter processing at the m sampling time (t-1) K is completed. can get.

(6) Next, this calculated value ff)-Ktt・8PD(t-
j) in the register RIK, the write control signal WRI indicated by the contents of RG+a; R1 wal ; @1' (wnxtic) is written to the operating code O
As a PC, register number information ROn is also output from the control signal output register 303.

As a result, the arithmetic circuit 4020 output data [11・J
IPD(t-J) is stored in register RIK.

(7) Next, rounding to view the amplitude data 8PD (t-j-1) of (j-1) time ago from memory 8DO, DLm i
DLm DLk g DLID GP2; @1' L2 蕃@1" (LATCH) Memory type information @DLk, latch control No. 41 L1. Gate pulse signal GP2 runs 1 as the operating code OPC, and the memory number Information DLm is output from the control signal output register 303. Then,
The address information output circuit 30B sets all bits of the lower address information to @O" and stores memory number information DLm in the higher order.
Add +(-DL・) and memory type information DLk (ml 9th D), address information DM for memory 80OK
・Output as mu DI. Accordingly, the amplitude data 8PD (t-j-1) of (j-1) hours ago is stored in the memory 80G.
is read out and latch l0IK is latched.

(II) Next, register jl 11 O contents Kst @
8! 'D(t j )e coefficient Its, latch Igl
Amplitude data latched in l/B PD (t-
J-1) R1 snow/11PD (t-j-1) +(
ill)' and store this calculated value again in the register wing IK. First, the latch control signal L1 of the content is indicated by Ram g RI Lli@l" (LATCH) and is stored in the register wing IK.
As code OPC, register number information -1GI+ is output from control signal output register SO1, register 1
1, IFKII/gpD(t-j) is latch 4114
will be forwarded to.

(9) Next, Kls -11PD(t-J-1)+(R
In order to perform the calculation of 1), MuDR(K wing); MuDR(Klm) ILI; 81LICT#)CTL
Content O signal 11L1. II'rL is an operating system;-doO
As a PC, nine address information modules DR(Th) are output from the control signal output register sOs.

Due to the slippage, the coefficient section is read out from the coefficient memory 400 and supplied to the operation input card of the operation path 4He. 9, the selector 401 selects the amplitude data 8PD (t-J-1) that is present in latch 1 and IKff, and outputs it to the arithmetic circuits 4 and 2.
(to the calculation input of ). As a result, the operation block 4
・2 is (a) Maro■・ni)+-) Tomigo 1 snow-5in (*-j-1)+K11・5pa(t
-j) Output the O calculation value (1). Then, this calculated value (a) is stored in register/1ITh and R1 in the next O step, so the contents of register wing 1 and R20 are 1 error 4ν'D(t
-j-1) Ichiban → I [凰1・8PD(t-J).

a.Next, register! O inner spring, coefficient In, mail ID
0K memorized (j-1) hours ago otM transmission data tD (t-j-1)K, Its -11PD (t
-) 1) + @'R) Rounding to perform O operation, ★S, amplitude data IPD (
t-j-1) is read from Memine 11DO, latch 10
It is latched to 1.

R9 Next, transfer the contents of the register iso to the latch 404, and transfer the contents of the register wing 20 Lsli'D(t-J-1)+K in the same way as the b-(8) OJ step described above.
o4FD(t-J) is transferred to latch 404.

1m5cK, coefficient] Read out c13 and get Kss-111'
D(t-j-1)+(To perform 1-0 operation, DIE[]Cm); ADR([18)ILI
g81LIC? @)CTL gcr)*
■・■+-) Signal 8L1. C? L is the operating mode OPC, and address information (D group X) is also output from the control signal output register 303.

As a result, the coefficient V4@0 or the coefficient -1 is read out and supplied to the arithmetic circuit 402@arithmetic input.

Then, the data 401 selects the amplitude data aPD(*-j-1) held in the latch l0IK and supplies it to the arithmetic input 00 of the arithmetic circuit 4020.

As a result, the arithmetic circuit 402 is (A) 2)・■+−)
The calculated value of t-j) is output. And this calculated value (
B) is stored in Regis J#]12 in the next step, this register l! Bypass filter 1py6c is provided through.

In the final step in the a10-pass filter LPPK, write the contents of register Otori 1 to 80OK, and then write
Rounding to be used in m(t+1) when printing, first register 110 contents rKu-jiPD(t-j-1)+1ct
After t・IPD(t-J)J is transferred to the latch 404 in the same step 11 as in step b-(8) described above, the arithmetic circuit 462 is caused to calculate m-), and the calculated value ``( stomach)
11811m・IIFD(t-J-1)+ICt IP
D(t-J) J;J>! / 4 Re8DOK is written. Jin's write operation is DLs i DL・DLkg DLs.

This is done by outputting the operation decryption code opc and the number information DL to be printed from the control signal output register SO1.

When the operations of the low-pass filters I and PF are completed, the operation of the bypass filter HPFO is performed next, but a description of the operation of the high-pass filter HFF will be omitted.

Next, the operation of forming the target reverberation sound IVD 1 at the delay time interval will be explained.

Forming operation of O0 reverberant sound VD" *** When forming ti, (1) If, bypass filter lFF0 Storage data corridor pDCt of register wing 4 pDCt-J) Multiply by K coefficient Ksv, and the multiplied value Ksy- JIPD(t j)・Register R5
The latch control signal L1 and the register number information wind G+a with the contents shown by Gm1R4 Ll Black 11" (LAtch) are output from the control signal output register SO1, and the contents of the register R4 are 1iFD (t-J). is transferred to latch 4@4.

(8) Next, rounding to calculate K11.8PD(t-j), ADI(Km); MUDR(Kn) sx, x i jllcI, IC? (e)CTL
i(1')-)・■ Select control signal aL1. Calculation control value number C? L, address for reading coefficients D (Km)
is output from the control signal output register 30s.

This is K], the coefficient 1 is read out from the coefficient number 9400 and supplied to the arithmetic circuit 4 (IfO arithmetic input).

First, the controller 401 selects the data 5pD(t-j) latched in the latch 404 and supplies it to the arithmetic input 00 of the arithmetic circuit 402 .

As a result, the operation path 402 becomes (j)m(4-(g)swKttlPD(t j)O
Outputs the calculated value (a). This calculated value (a) is stored in register 8 in the next step.

(3) Next, the amplitude data 5 of 11 hours ago is stored in the memory D1.
PD(tll) is taken out and this data IPD(t-xt
) and the current value of register 114D, and the added value is stored again in register RI IK. First, DL
■! DLI DLk; DI, +.

Lm; “1” (I, A’l”CH) L snow; “1” (LA’rCH) The latch control signal L3, IJ with the contents indicated by “1” (LA’rCH), the serial number information DLm and the memory type information DLk are It is output from the control signal output register 303.

As a result, the output information ADR (Di) of the address column C (DI) corresponding to the memory DIK is changed to the amplitude data 1i
It is latched into the latch 80@ as lower address information for generating FD (t-it). This lower address information ADR (DI) is sent to the address information output circuit 301.
At this point, message number information DLm and memory type information DLk are added to the higher order and outputted as message DIO address information DR for data mail 10@. As a result, the amplitude data IIPD (*-xs) of 11 hours ago is read from the message Dl, and the latch l0
IK is latched.

(4) Next, rounding is performed to add this start-up data apD(t-(t) and the current value of register R11O.
1 t) After the contents are transferred to the latch 404, 8L1
g ggx, gct@) C? Li(1')! (1) +-) The select control signal 11L1 and the calculation control signal CTL having the contents shown in the following are output from the control signal output register 30s.

Then, the selector 401 selects the latched amplitude data gPD(t-XI) and supplies it to the calculation input 00 of the calculation circuit 4gH. This is K], operation-
Road 402 is cr + fable (2) Jutogami (111) + 1lFD (t -1
) is output to the calculated value indicated by 1'). In this case, the contents of register Ill10 are the previous O sampling time (t
-1) It is cleared at the stage when the K setting operation is completed.

In this ninth step, the calculated value (7) at step 14)K becomes 8PD (tlr).After this, the calculated value (7) is transferred to the register 111 and stored.

(5) Next, amplitude data 8PD (t-i
t), multiplies it by the coefficient KII, and then adds the 70 multiplication value C・8PD(t-xt) and the contents of register 1B, Ward 1! - Rounding to store the 5pD(t-j) J and O addition value in the register 16 again. First, in the same aircraft as the step - (1) described above, IFrKty in the register wing 5.
8PD(-j)" is transferred to latch 4.4.

(Shunji, the amplitude data that is latched by l0IK)
IPD (tlt), the data latched in the latch 404 "K weight!・5pD(t-j)J - coefficient Kxs
Toyo), (rimKss-11PD(t-!1)+Ku
-gFD(t-j)O operation, MuDR(Ka) *MuDR(Kll) ILI ill LIC'r(II)C'l'L
The contents indicated by iYusho), Ni)+-), the select control signal JiL1, the arithmetic control signal CTL, and the address information 11 (Lm) for reading the coefficients are output from the control signal register SO3.

As a result, one coefficient is read out from the coefficient memory 400 and supplied to the arithmetic circuit 402t).

First, the selector 401 selects the amplitude data gPD (tlt) latched in l0IK and sends it to the arithmetic circuit 40.
2 to the calculation input 00.゛According to this), the arithmetic circuit 402 is v') to (2)・■+(to) mKts・1iPD(tlt)+Ku4PD(t−j)
Output. Then, in the next step, this calculated value (A) is written to the 9th address corresponding to the memory DiOII present time t via the register R6. After this, the register wing 6 is cleared for the ninth time to dispose of the system in the memory D2.

1γ) Next, the processing for each system of memories 9D2 to D9D is performed in the same way as the steps of -(3) to -(6) described above, and the process for each system of memories D1 to D9 is When the layer is completed, the register blade 11 obtains information regarding the reverberant sound group IK represented by .

Next, the operation of forming reverberant sound RVD with dense delay time intervals will be explained.

d. When forming the reverberant sound formation operation ``VD'', (11th, amplitude data 11 hours ago from Memo 9 MDO) R
To read "VD" (t-yt), DL So; DL・DLk i DLMD L3; @1' (L whip C1) L2i@l
The latch control signal -?L3.Ll with the contents indicated by ``(LA?CH), memory number information DLn, and memory type information DI, k are output from the control signal output register 30s. In the address information output circuit 301, the above-mentioned meeting (3)
) Address information DM・MUD8 for the memory MDOK is formed in the same way as in the step 11 from the memory MDO.
The previous amplitude data RVD" (t-yx) # is read out. Then, this data RVD" (t-yl) is latched into the latch 101.

(21 Next, the nine amplitude data R latched in the latch 101
VD”(t-yl)I register XI R11O output f-)
IVD''(t), coefficient Ks@ calculates pl Kao-RVD'(t-yl)+RVD''(t), and stores the calculated value in register R1! At the ninth stage, the output data wing VDI (1) of register R11 is transferred to the latch 404K, and after that, the output data wing VDI (1) is stored in the register R11.
Kit) BLl; glLIic? (1) CTL
;-(4)・ni)+-) Select control signal 8L1. The arithmetic control signal CTL and the address information DB (Km) for continuous coefficient output are output from the control signal output register SO3.

As a result, the coefficient Is is supplied to the p1 arithmetic circuit 402 as the arithmetic input (A)K in the same way as in step (6) above, and the data VD'' (t-71) is supplied as the arithmetic input ( b).As a result, the arithmetic circuit 482
r)-(transition)・■+-) m 1css-11VD"(t-yt)+IIVD"(
t) Output the O calculation value (a). And this calculated value (
A) is stored in register 12 at the next OX step KsPvh.

(3) Next, register lN12t) Contents rKn・RVD”
(t-ys)+]lVD”(s) Rounding to multiply J by the coefficient Kms, first the contents of register 1111 are set to latch 4.
After being transferred to 04, ADa(In)iADa(Kss) 11LI Knee 111LIC'r(C)CTL
The select control signal ILI with the contents indicated by 1 (IQ book (4)), the calculation control signal C'f'L, and the address information DiL (Kn) for successive coefficient output are output from the control signal output register 30s. be done.

Accordingly, the coefficient Is· is supplied to the calculation circuit 402, and the data r1cm···RVD” (t
-Fl)+RVD'('l is supplied to the arithmetic input 4. The arithmetic circuit 402 is a bacterial genus ^・(1) -Ks+s ・[Kao -RVD' (t-yx
)+RVD''(t) ) is output. This calculated value (a) is stored in the register 113 in the next step.

(4) Next, add the contents of register R13 and the data avn" (*-yt) 11 hours ago, and round to store the added value again in register 113, as described above Od - (1)
Similarly to step 0, the data 11 hours ago /RVD'' (t-Fl) is read from the memory MDO and the latch 1 is read out.
It is latched to 01. After this, register R130 contents r
K 禦・(Kso-RVD” (t-yx)+RVD”
(t)) After J is transferred to latch 404, 11LI; 111LICT(II)C? L;(1'
) The control signal gL1 and the calculation control signal CTL are outputted from the control signal output register sos. As a result, the p1 arithmetic circuit 402 becomes ff)-II)+
ni) wiivn'(s-ys) +Ku ・(Ks* -RVD' (t-y i)
+RVD '(愈)) The calculated value (A) is output. This calculated value is stored in the register 113 at step CR) and is stored as reverberation sound information RVI).

<15) ecFc, 'gr- in VdiXlR120:
o, RVD” (toy1) +RVD1 (1) J to 1!
Since it is used in the case of large numbering m(t+yt) due to a time lag, the contents of the register R12 correspond to the time tK of memory MDO011 and are written to the friend address.

(8) After this, at 11 hour intervals), residual sound wings VDII and RVD are formed in the same manner.

In addition, although a bandpass filter is provided in the embodiment of the IIs diagram (Iris diagram 6), this may be omitted if necessary.
Finally, the memory D100 output data is divided into three frequency bands: bypass filter npy, pandobus film IFF, and low-pass filter LPPK. I
It is possible to form different reverberation sounds for each frequency band in the 41 sound formation section 2. This can be easily achieved by simply modifying the contents of the control program.

Further, in the above embodiment, the delay circuit is constructed using a digital system, but the delay circuit 1 can be constructed arbitrarily, and BIID-? such as CCD. According to the present invention, as described above, K is constructed to utilize an anada delay element. The 1K reverberant sound adding device is a combination of a delay circuit that forms 1141 sounds with irregular polishing times and levels, and a delay circuit that forms Mj11M reverberant sounds with delay times and levels. For this reason, the naturalness that can be obtained at a concert hall, etc. +Reverberant sound can be generated with a small-scale configuration. First, if a digital memory is used as the L circuit, 8/)i will not decrease even if the residual time is increased, and it will be possible to fake reverberation with good quality.In the case of ζ0 To change the address interval of the digital meter to change the % reverberation interval, change the reverberation sound according to various internal conditions. There is an advantage in that it is difficult to carry out **.

[Brief explanation of the drawing]

111#i Typical t1 of conventional reverberation sound adding device
1 shows the configuration, 2 shows the impulse response 411
Seikaku and Shōsankaku are impulse response characteristic diagrams of 1lIl 轡音 for concert halls, Shōkaku 1 diagram showing other examples of conventional reverberant sound adding devices, 1a#ijin Due to the origin! II A plotter diagram showing an embodiment of the sound adding device; Fig. 6 shows the embodiment of Fig. S functionally; Fig. 7 and Fig. S show the basic configuration of the delay circuit; 1011 is a plotter diagram showing the 0% initial reflection sound generated in the embodiment of FIG. Lid filter configuration OjI En-ro 011a
& Figure 811 is a characteristic diagram of the reverberant sound generated in the embodiment shown in Figure S, and Figure 14 is a diagram showing the structure of the data memory in the embodiment shown in Figure 6.
+Hs diagram is a diagram showing the structure of the delay length data memory in the embodiment of FIG. 5, 10611 is a diagram showing the structure of the address callan 10 in the embodiment of FIG. It is a functional block diagram showing an example. 1. Initial reflection sound formation section, 2.. 1st reverberation sound formation section, 3.. - 2nd reverberation sound formation section, BPF.. 4#0
Hand pass filter, 1...Storage section, 20@...
Time information generation section, 3...Address information generation section, 4
...Calculation section. Pardon applicant: Japanese Qin 1! Itzo Co., Ltd. Dairuhito Masaki Yamakawa 01 or 1) No. 1411 ~ / 00 PSLtlS Garden

Claims (1)

[Claims] (1) A 10th delay wA- which outputs a plurality of input sound collection signals with different delay times and six selection delay times;
Upper I! ! - It has a level control circuit that controls and outputs the O level of each Oaa and Qin Yin Yu, respectively - and a feedback loop that returns the self O transition output to the input side, and has a feedback loop that returns the input image and sound signal and the self The output signal of the level control circuit and the 11110 extension circuit are combined in a predetermined ratio with the output signal of the level control circuit and the output signal of the 11110 extension circuit in order to output a good signal with a predetermined time delay. 0 output signal and input the synthesized signal to the electric sound signal 0.
A synthesis circuit and a reverberation sound adding device to output the residual **reverberation as a true value. (■ Change the input image sound signal to a different length and output multiple OjI Enhata sound signals. It has an output corner level control circuit and a J1 feedback loop that returns the self-0 delay signal output to the input side, and synthesizes the input image sound signal and the self-0 delay signal output at a predetermined ratio to produce a good signal. A third input signal is outputted at a predetermined delay time, and the input image and sound signal is outputted far from the plurality of delayed sound collection signals.
The first soj that can be input to the ejI tokiro! A grinding circuit and a synthesis circuit that synthesizes the level control circuit O output signal and the tenth extension O output signal and outputs the synthesized signal as a reverberant sound signal of the input sound collection signal. A reverberation sound adding device.