JPS60169954A - Memory access system - Google Patents

Abstract

PURPOSE:To increase the number of address lines practically and to expand the access space of a memory by triggering a latch by an output from a decoder and latching a signal on a data bus by the latch. CONSTITUTION:At the writing of data in the memory 11, a specific address is supplied to the decoder 13 and the latch circuit 12 latches data (false address signal) on the data bus line L1 on the basis of the decoded output. When a prescribed address signal and writing data are sent, the memory 11 is accessed by the precedently latched output and the current address and data are written in the address. At the reading of data from the memory 11, an address is specified similarly and then a read signal is supplied to read out the data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a memory access method in an information processing device such as a microphone quad processor, and particularly to a memory access method capable of expanding (extending) memory access space. ◇Generally, if the use of address lines for specifying memory addresses is restricted, the accessible memory space will decrease accordingly, so it is desirable to compensate for this by some means.

[Prior art and its problems]

In general, the accessible memory space in an information processing system depends on its address line If (K. For example, if an 8-bit microprocessor has a maximum of 16 address lines, 21
6, that is, 64 bytes of memory space can be accessed. However, if these address lines cannot be used fully, for example, 8 of the 16 address lines can be
If the memory space is used for decoding to select 10 (input/output devices), and there is a restriction that only the remaining 8 can be used, only 2, that is, 256 bytes of memory space can be used. Conventionally, methods for expanding the memory access space in such cases include, for example, using another microphone processor or adding a control circuit to secure address lines for expansion. ing.

FIG. 1 is a block diagram for explaining an example of the latter memory expansion method, and FIG. 1A is a detailed block diagram showing the main parts of FIG. 1 in detail. is bidirectional t<S N7, 3.4 is the decoder, 5
is P P I (ProgrammablePerip
heral interface element; has a general-purpose input/output interface function for connecting peripheral devices to the system bus, and is programmed by the system software. ), 61 to 65 are memories.

Now, of the 64-byte memory space, for example, up to 52 bytes can be accessed by a circuit not shown.
It is assumed that a memory space of the remaining 12 bytes is created using the illustrated circuit. AB is an address bus, and for example, two of these path lines (PAL) are used to route PP15, and the rest are used for decoder 4 to generate chip select signals Cal to C85 to be applied to memories 61 to 65. A data bus DB that provides data to the memory is connected to the PPl5 and the memories 61 to 65 via the buffer 2. In addition, the memories 61 to 6
5 to each address line AL2. AL3 and data bus DB2 are connected, but they are shown together here. As shown in the first Alffl, details of P P, I 5 include a buffer 51, a thick circuit 52 for control, group control circuits 53 and 54, latches 55 to 58, and the like. The control p-thick circuit 52 is for controlling which latch is used among the plurality of latches 55 to 58 serving as output ports.
Control circuits 53 and 54, which perform group control of the latches 55 to 58, are controlled based on the signal on the line PAL mentioned above and read and write signals (not shown).

Here, in order to obtain the address signals of the memories 61 to 65 via the boat outputs POI to 4 of PPl5, PPl5
The symbol on the address buffer is introduced into the address buffer as a control signal, and the data bus line signal is applied via the buffer 2, and this is sent to the latch circuits 55 to 5 of the PPl5.
It is also necessary to latch the input signal ALL of the decoder 4 for creating the memory selection signal (chip select signal C5I~5), and by doing this, the memory can be reduced to only 52 bytes. Even if access is not possible, the memories 61 to 65 allow expansion to a desired space.

However, according to such a method, a) address lines are generated by I10 port outputs P01 to P04, so data signals are latched by latch circuits 55 to 58 inside PPL5, and data bus signals are Only the number of bits specified by the number of address lines and the number of memory selection signal lines must be sent and latched.Furthermore, in order to create the address signal (ALl) that generates the memory chip select signals C81 to C85, data must be sent and latched. It is necessary to latch the bus signal inside the PPI. Therefore, control becomes complicated and high-speed data processing is not possible.

0) The number of control elements including PPI elements increases, resulting in high cost. Furthermore, the former method using another microprocessor has the disadvantage that both the hardware and software become complicated and expensive.

[Purpose of the invention]

The present invention has been made to eliminate such drawbacks, and an object of the present invention is to provide a memory access method that is easy to control and capable of high-speed data processing.

[Key points of the invention]

At the ff point, a decoder and a latch circuit are provided between the processor and the memory, and the output obtained by decoding a predetermined signal on the address line is given to the latch circuit to latch the data signal (pseudo address signal) on the data bus line. By accessing the memory based on the latch circuit output and a separately provided address signal, the actual number of address lines is increased and the memory access space is expanded.

[Embodiments of the invention]

FIG. 2 is a configuration diagram showing an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining its operation. In Figure 2,
11 is a memory, 12 is a temporary storage (latch) circuit, and 13 is a decoder. Although the processor is not shown in the figure, it is an extension of the data bus line L1, address bus line L2, read signal line L3, write signal fmL4, etc., and includes, for example, an 8-bit microprocessor. shall be.

Here, assume that there is a restriction that 12 of the 16 address bus lines are used for other purposes and only the lower 4 lines (4 bits) are provided to the memory 11. The accessible memory space is only 24, ie, 16 bytes (addresses 0 to 15). At this time, if a larger memory space is required, for example 2 bytes of memory space, a total of 12 address lines will be required, resulting in a shortage of 8 lines. Therefore, in the present invention, in order to form the missing eight address lines, the signals on the eight data bus lines Ll are latched by the latch circuit 12, and the address necessary for accessing the memory is It is designed to generate a part of .

When writing data to the memory 11, first, a specific address (for example, address xxxF) is given to the decoder 13, and the decoder output is used to write the data (pseudo address signal) on the data bus line Ll. The latch circuit 12 latches it. Next, by sending out a predetermined address signal and write data, the memory 11 is accessed using the previously latched output and the current address, and data is written at that location.

For example, when writing 8-bit data 7F'' to address ``0106'' in hexadecimal notation, as shown in Figure 3 (A), first write 1XXXF'' (see Figure 3) to address bus L2, then write the data The data ``[0'' (see O in Figure 3) is sent to the bus L1 from a processor (not shown), and a write signal (see O in Figure 3) is sent to the bus L1.Then, the address bus L2 is sent ``XXX6'', The data ``7F'' is sent to the data bus L1, and a write signal is sent to the data bus L1.In this way, the data ``7F'' can be written to the desired address position by two operations. If you want to write, you can repeat the above operation.Also, to clear the latch output, send '00'' to the data bus L1, as shown in Figure 3, or provide a control terminal to the latch 12. This is done by sending a clear signal through the control terminal.

The case of reading data is the same as above, but in this case, as shown in Figure 3 (B), after specifying the address in the same way, a read signal as shown in Figure 3 (■) is given, and Clearing the latch output is performed in the same manner as above, except that the data of O is read out. In addition,
Signals ■, ■, θ, O in FIG. 3(A) and signals ■, @ in FIG. 3(B).

0/ and 0/ correspond to each other.

In this way, the accessible space of the memory can be expanded with simple control circuits and control procedures. Note that in the above example, address 'xxxF' cannot be used as a memory access area, but there is no particular problem as the area that can be compensated or expanded using the data bus is much larger. In addition, although the above example describes the case where there is one memory, it goes without saying that the memory access area can be expanded in the same way even when there are multiple memories.Furthermore, the above example uses a microprocessor. Although described above, the present invention can be widely applied to information processing devices similar to this.

〔Effect of the invention〕

According to this invention, a decoder and a latch are provided between a processor and a memory, the latch is triggered by the decoder output, and the signal on the data bus (pseudo address signal) is latched by the latch, thereby controlling the address line. This brings about the advantage that the number of memory cells can be substantially increased and the memory access space can be expanded. At this time, the necessary circuit elements are basically only decoders and latches, so not only can costs be significantly reduced compared to the conventional case of using other processors or PPIs, but also the circuit elements required are The configuration and control method are simple, and it is possible to improve processing efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional memory expansion method, Kasumi IA diagram is a detailed block diagram showing the main parts of FIG. 1 in detail, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. The figure is a waveform diagram for explaining the operation of FIG. 2. Code explanation t t z t s i...Buffer, 3, 4
．． 13...7': l-ta, 5...PP
I, 11.61-65...Memory, 12.55
~58... Latch, 52... Control logic circuit, 53, 54... Block control circuit. Agent Patent attorney Akio Namiki Agent Patent attorney Kiyoshi Matsuzaki S Figure 2

Claims (1)

[Claims] In an information processing device having at least a processor and a memory, there is provided a decoder for decoding a predetermined address output from the processor via an address bus; The present invention is characterized by providing a storage means for temporarily storing the output pseudo address, and expanding the accessible memory space by accessing the memory based on the storage output and the address separately output from the processor. Memory access method.