JPS60169970A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To compensate and increase the memory access space between processors in a multiprocessor system while preventing data from collision by forming an address generating means and a bus control means. CONSTITUTION:An address signal supplied to a selector 16 consists of 4 bits and an access space of a common memory 15 consists of 16 bits. If eleven address lines 11 are supplied from the processor 11 to the selector 16, the memory space can be accessed up to 2K bytes and imbalance is generated in the quantity of data communication in a normal system. To remove the imbalance and to use the same memory space as the processor 11, a signal on a data bus DB2 is stored in a temporary storage element 21 by using a decoder 22 and the stored signal is combined with the address signal to supply the combined signal to the selector 16. Thus, the memory access area can be expanded.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention relates to a so-called multiprocessor system consisting of a plurality of processors, and in particular, to improve efficiency by balancing unbalanced amounts of data communication between processors that perform data communication. The present invention relates to a multiprocessor system that enables good data communication.

[Prior art and its problems]

FIG. 1 is a block diagram showing a conventional example of a memory access space expansion method using a single processor. In the figure, 1 and 2 are buffers, 3 and 4 are decoders, and 5 is a PPI (Programmable
Peripheral Interface element: A device with general purpose input/output interface functions for connecting peripheral devices to the system bus, and is programmed by the system's software. ), 61 to 65 are memories.

Here, in order to access the memories 61 to 65, address line LA1. It is necessary to provide a predetermined address on LA2, and this address is generated by causing six latch elements (not shown) inside PPl5 to latch predetermined data. Each latch element can input/output 8-bit information, and designation of this input/output is performed by programmable means. Above 6
When one latch element is designated as an output port, the total number of output bits is 24, so 16 bits are used as address signals, and 8 bits are used to generate memory selection signals C81 to C5 by decoder 4 (signal line LA3). reference)
If required, the memory can access up to 216, or 64, bytes, and the memory select signal is 2
41, that is, u256''. To make such a specification, it is necessary to write and send predetermined information six times to the inside of PPl5 via data bus DB and buffer 2. In other words, ' It is necessary to latch the signals on the eight data bus signals twice to create a 16'-bit address line, and to write the data signal once into the PPl5 to create memory selection information. In other words, this method has the advantage of being programmable, but this makes the control complicated and takes time to access the memory, making it difficult to perform high-speed data processing. I can't.

Mouth) There are many peripheral elements for control, including PPI, and the cost is high.

c) When applied to a multiprocessor system, not only does the circuit become even more complex, but also the problems in item 1) have an even more complicated effect.

There are some difficulties.

Furthermore, even if this method is suitable, applying the memory space expansion method for a single processor to a multiprocessor system not only complicates the control associated with data communication but also complicates the circuit configuration, resulting in high costs. There are disadvantages such as being expensive.

[Purpose of the invention]

The present invention has been made in view of the above, and it is possible to increase the amount of data communication relatively easily and inexpensively by making it possible to expand the memory access space of at least one processor that constitutes a multiprocessor system. The purpose is to provide a multiprocessor system capable of data processing.

[Key points of the invention]

In a multiprocessor system consisting of a plurality of processors, this invention generates an address to be given to a common memory by programmably temporarily storing a data bus signal using a decoder and a temporary storage (latch) element, and using this signal in combination with an address signal. an address signal line and data 2371 for use in data communication between each processor and the common memory;
Data collision is avoided by providing Yukihiko 5 bus control means for selection and switching of the No. 6 line and control path line using selectors and buffers. In a multiprocessor system, mutual memory access space between the processors, In other words, it is designed to compensate for or increase the amount of data communication.

[Embodiments of the invention]

FIG. 2 is a block diagram showing an embodiment of the present invention.

In the same figure, 11.12 is a microprocessor, 15
．． 25 is a control logic circuit, 14 is a control unit, 15 is a common memory, 16.17 is a selector, 18-
20 is a buffer, 21 is a temporary storage (latch) element, 22
is a decoder, 24 is an inverter), and 25 and 26 are OR gates.

That is, what is shown in the figure is the microprocessor 11.
．． Data communication between the 12 devices is performed via the common memory 15. Note that even when the number of processors is six or more, the address bus, data bus, and control bus for read and write signals are used as a common bus.
If you decide to connect another processor in parallel to this,
Regardless of the number of processors, it is basically the same as the case of two processors. Further, at this time, it is also possible to operate one of the processors as a master processor and the others as slave processors.

First, when accessing the processor 11.12df common memory 15, address buses AB1, 2, data bus DB1.2, control bus CB1. Selector 16,1 to distinguish between
7 is used. Note that the signals on the control bus CB1.2 include a read signal ItD, a write signal WT, and control logics 13, 2! There are control signals CT1, CT2, etc. output from the terminal. The signal that separates the processors 11 and 12, that is, the signal that controls which direction the selectors 16 and 17 are directed to, is SL, which is generated by the control unit 14. This control unit 14 is, for example, reset-
Set (R-8) A signal S consisting of a flip-flop circuit, a gate circuit, etc., and generated by latching the address decode signal and data bus signal from the processor 11.

The processor 12 performs predetermined processing in response to a signal SO2 generated by latching the data bus signals of the processor 12 and the like. In addition, the allocation of the data bus DB3 required when accessing the common memory 15 is, for example, a buffer 18, 1 consisting of a known tri-state buffer or the like.
This is done by controlling the opening and closing of gates No. 9.

In other words, the processor 11 is connected to the common N\memory 15 via the buffer 19 and the data bus DB3.1, and
The processor 12 has a buffer 18 and a data bus DB3.2.
Data is written and read through the respective memory terminals.

Next, a method for expanding the memory access space in such a multiprocessor system will be described. In addition,
Here, the processor is an 8-bit microprocessor, and in particular in the processor 12, 12 of the 16 total address bus lines provided are used for other purposes, and only those provided to the memory 15 are used for other purposes. Assume that there are only the bottom four. As a result, the address signal supplied to the selector 16 becomes 4 bits, and therefore the common memory 1
The access space for No. 5 is 24, that is, 16 bytes.

On the other hand, assuming that the number of address lines supplied from the processor 11 to the selector 16, and therefore to the address bus AB, is 11, 211. In other words, it becomes possible to access up to 2 bytes of memory space, which causes an imbalance in the amount of data communication in a normal system. Therefore, in this embodiment, in order to eliminate this imbalance and use the same memory space as the processor 11, the decoder 22 is used to store the data bus buffer signal in the temporary storage element 21. By supplying a combination of the storage signal and the address signal to the selector 16, the memory access area is expanded. At this time, the decoder 22 decodes the signal on the address bus line and supplies this signal to the element 21 as a synchronization signal for temporary storage, but this control is performed by the processor 1.
This is done programmably by 2. Note that this synchronization only needs to be performed once, and there is an advantage that it is not necessary to use an element that is expensive and complicated to handle, such as a conventional PPI element. In addition, in order to further develop this method, if it is desired to increase the memory access space from -10,000 processors (for example, even if there is no shortage of address bus lines, processor 11 can access 2 bytes, while processor 12 When you want to expand the access space (from 1 to 4 bytes), or when the address lines of both processors are restricted, you can expand the memory space by appropriately adopting the access method described above. can be achieved.

In the above example, it was assumed that the number of address lines supplied from the processor 12 was four, and the number of address lines supplied from the processor 11 was assumed to be 11, but the same procedure can be used for other numbers of lines. That's not true until number 5. Furthermore, if you want to further expand the memory space by increasing the number of address lines, you can do so by adding one decode signal from the decoder 22 and one temporary storage element, and this newly added temporary storage element It is sufficient to perform synchronization programmatically once.

Next, the division of the data bus will be explained.

In order to read and write data from the processor 11 to the common memory 15, it is necessary that the data bus buffer 18 be closed (cut off) and the buffer 19 be opened. Therefore, by applying the switching signal SL to the buffer 18 via the inverter gate 24 and directly to the buffer 19, the buffer 19 is enabled.
When the buffer 18 is in the ble state, the buffer 18 is in a disabled state. The OR output of the switching signal SL and the memory selection signal C8 is given to the enable terminals of the buffers 18 and 19, and this selection signal is sent from the processor 11 (12) to the control logic circuit [13 (23) and the selector 17]. For example, it is enabled when it is at a low (L) level. In addition, the buffer 18
．． The directionality of 19 is determined by a memory write signal WT obtained via selector 17.

On the other hand, the processor 12 also reads and writes data to and from the common memory 15 in the same manner as described above, but the logical relationship is reversed. That is, by reversing the logic of the switching signal SL that controls the buffers 18 and 19, the buffer 18 is opened and the buffer 19 is closed (cut off).
In this case, the data on the data bus DB2 is temporarily stored in the temporary storage element 21 in order to compensate or expand the memory access space as described above, or is used for data communication between the common memory 15 and the processor 12. It is necessary to distinguish between the two. Therefore, when a specific address is programmably given, for example, a code in which the lower 4 bits are all 'H', that is, an address code of "X X X F" in hexadecimal notation, the data on data bus DB2 is used as the address This distinction is made by temporarily storing data in the temporary storage element 21 for the purpose of accessing the address, and by determining that common memory access is required for other addresses.

In this way, it becomes possible to expand the memory access space and control data communication in the common memory. However, although the above-mentioned specific address used to expand the memory access space becomes unusable, the space gained by expansion is much larger than the space reduced by this, so there is more than enough space to compensate for the drawbacks. It is something.

FIG. 6 is a partial configuration diagram showing a modification of FIG. 2.

This is because the buffer 18, which was connected to the data bus DB2 via the buffer 20 as shown in FIG. The switching signal SL and the selector signal CT2 issued from the control logic 23 are connected to one of the OR gates 25 provided at the enable terminals.
is introduced via an AND gate 60. That is, two buffer games) 18.20 open,
This is for controlling the closing by the control logic 23, which eliminates the need for address extension by data bus signals according to the specification of a specific address, and the use of other address common memory, and allows programmable processing from the processor 12. By controlling the gate of the buffer 18 through the control logic 23, the same function as described above is provided. Note that all buffers are bidirectional, and for example, the directionality can be determined by the read signal RD1.degree.2.

〔Effect of the invention〕

According to the present invention, in a multiprocessor system, a data bus signal from at least one processor is programmably stored in a temporary storage element and a decoder that generates a signal for synchronizing the data bus signal, thereby creating a pseudo address. By increasing the number of lines, that is, by increasing the data communication space, and by supervising the usage of common memory by multiple processors, data collisions can be avoided and data This brings about the advantage that communication can be carried out efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a memory address expansion method in a conventional single processor, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a partial modification of FIG. This is a diagram. Code explanation 1, 2t1B~20...Buffer, 5, 4, 2
2...;...decoder, 5...PPI element,
61-65... Memo L11, 12...
Processor, 13, 23... Control logic, 1
4... Control unit, 15...
・Common memory, 16, 17...Selector, 21
...Temporary storage element (latch), 24...
・Inverter gate, 25, 26...OR gate, 60...AND gate. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki Figure 3

Claims (1)

[Claims] In a multiprocessor system in which data is exchanged between a plurality of processors via a common memory, at least one of each processor includes a decoder for decoding a predetermined address outputted from the processor via an address bus; storage means for temporarily storing a pseudo address outputted from the processor via a data bus in response to the output as a synchronization signal, and a storage means for temporarily storing a pseudo address outputted from the processor via the data bus, and a storage means for temporarily storing a pseudo address outputted from the processor via the data bus, A multiprocessor system characterized by compensating for or expanding an accessible common memory space by performing access.