JP3436497B2 - Memory access circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a dual port R
The present invention relates to a memory access circuit for reading and writing a memory such as an AM (random access memory).

[0002]

2. Description of the Related Art FIGS. 2A and 2B are block diagrams of a system using a conventional dual port RAM, in which common elements are designated by common reference numerals. In the system of FIG. 2A, the dual port RAM 10 has, for example, 25
A storage unit 11 having a storage area of 6 words × 8 bits;
Two ports 1 for accessing this storage unit 11
2 and 13. Each port 12, 13
Data can be written in and read from the storage unit 11 independently. The port 12 has, for example, a central processing unit (hereinafter, “CPU”).
20) and other functional blocks are connected via an 8-bit address bus 21, an 8-bit data bus 22, and a several-bit control bus 23. Also, port 1
3, a functional block such as a communication processing device (hereinafter, referred to as “CCP”) 30 is connected via an 8-bit address bus 31, an 8-bit data bus 32, and a several-bit control bus 33. There is.

In addition, this system has a CPU 20 and a CC.
The P30 has a control circuit 40 for avoiding simultaneous access to the same address of the RAM 10. The control circuit 40 has address buses 21 and 31 respectively.
Of the decoders 41 and 42, and a 256-bit data latch 43 connected to the output side of the decoders 41 and 42 for holding the decoding result. Data latch 4 from CPU 20 and CCP 30
3, a write control signal WE for writing the decoding results of the decoders 41 and 42 is applied. Further, when the decoding results of the decoders 41 and 42 and the data stored in the data latch 43 match, a wait signal for inhibiting access to the dual port RAM 10 from the data latch 43 to the CPU 20 and the CCP 30. WA is output.

In such a system, for example, CP
When U20 accesses the address A of the dual port RAM 10, it first outputs the address signal of the address A to the address bus 21. The address signal output to the address bus 21 is decoded by the decoder 41 and one bit corresponding to the address A becomes the logical value "1". Decoder 41
The result of decoding is given to the data latch 43, and it is determined whether or not it matches the data stored in this data latch 43. Here, if the decoding result of the decoder 41 and the data of the data latch 43 do not match, the wait signal WA is not output from the data latch 43.

If the weight signal WA is not output, C
The PU 20 outputs a write control signal WE to the data latch 43. As a result, the decoding result of the decoder 41 is written in the data latch 43, and it is displayed that the address A is being accessed. Subsequently, the CPU 20 reads / writes 8-bit data from / to the dual port RAM 10 via the data bus 22. When the access to the dual port RAM 10 is completed, the CPU 20 rewrites the bit of the data latch 43 corresponding to the address A to the logical value “0” and displays that the access is completed.

On the other hand, the CCP 30 is a dual port RAM
When accessing the same 10 addresses A, the address signal of the address A is similarly output to the address bus 31. The address signal output to the address bus 31 is decoded by the decoder 42, and one bit corresponding to the address A becomes the logical value "1". The decoding result of the decoder 42 is given to the data latch 43, and the data latch 43
It is determined whether or not the data matches the data stored in. If the CPU 20 is accessing the address A, the bit of the data latch 43 corresponding to the address A is "1".
Outputs a weight signal WA. Weight signal WA
Is output, the CCP 30 outputs the wait signal W
Access to address A of dual port RAM 10 is postponed until A stops. As a result, simultaneous access from the CPU 20 and the CCP 30 to the same address of the dual port RAM 10 is prohibited, and the validity of the data can be maintained.

In the system of FIG. 2B, the dual port RAM 10A comprises a storage section 11A having a storage area of, for example, 256 words × 10 bits, and two ports 12A and 13A for accessing the storage section 11A. It is configured. 10 forming one word of the storage unit 11A
Eight bits out of the bits are data bits for storing data similarly to the storage unit 11 in FIG. The 9th and 10th bits are for ports 12A and 13 respectively.
This is a flag bit for indicating that the access from A is being performed.

Each of the ports 12A and 13A can independently access the storage section 11A. A functional block such as a CPU 20 is connected to the port 12A via an 8-bit address bus 21, a 10-bit data bus 22A, and a several-bit control bus 23. The port 13A has a CC
A functional block such as P30 has an 8-bit address bus 3
They are connected via a 1- or 10-bit data bus 32A and a several-bit control bus 33. In such a system, for example, the CPU 20 has a dual port RAM.
When accessing the A address of 10A, first, the address signal of the A address is output to the address bus 21, and the data of the A address of the dual port RAM 10A is read. Then, 10 of the read 10-bit data are
The flag bit of the bit is checked to determine whether the CCP 30 side is accessing the address A of the dual port RAM 10A.

If the access from the CCP 30 side is not made, the fact that the CPU 20 is making an access is displayed by writing "1" to the flag bit of the 9th bit of the data at the address A of the dual port RAM 10A. . Following this, the CPU 20 sets the data bus 22
Access the dual port RAM 10A via A. When the access to the dual port RAM 10A is completed, the CPU 20 rewrites the flag bit of the 9th bit of the data at the address A to "0" and displays that the access is completed.

On the other hand, CCP30 is a dual port RAM
When accessing the same address A of 10A, similarly, the address signal of the address A is output to the address bus 31,
The data at address A of this dual port RAM 10A is read. Then, the flag bit of the 9th bit of the read 10-bit data is checked to determine whether the CPU 20 side is accessing the address A of the dual port RAM 10A. Where the CPU
If 20 is accessing address A, then address 9
Since the flag bit of the bit is "1", C
The CP 30 delays access to the dual port RAM 10A until this flag bit becomes "0". This prohibits simultaneous access from the CPU 20 and the CCP 30 to the same address of the dual port RAM 10A,
The validity of the data can be retained.

[0011]

However, the system using the conventional dual port RAMs 10 and 10A has the following problems. In the system using the dual port RAM 10 of FIG. 2A, in order to prevent access conflict, a data latch 43 having the same number of bits as the number of words (256 in this case) of the storage unit 11,
Since it is necessary to provide the decoders 41 and 42, there is a problem that the circuit scale increases as the number of words increases.

On the other hand, the dual port RAM shown in FIG.
In a system using 10A, this dual port R
Since the flag bit is provided inside the AM 10A, an access for checking and rewriting this flag bit is required, which causes a problem that the processing time becomes longer than that of the system of FIG. 2 (a). . The present invention provides a memory access circuit that solves the problems of the above-mentioned conventional techniques and that has a small circuit scale and that does not affect the processing time, in order to prevent access competition for dual port RAM and the like. To do.

[0013]

In order to solve the above-mentioned problems, a first invention of the present invention relates to a common storage area independently from an arbitrary address from first and second ports. The first and second memory access circuits connected to the first and second ports, respectively, for accessing the read / write access dual port memory are configured as follows.

The first memory access circuit holds a first access address to be output to a first port and gives it to the second memory access circuit, and the first access address. A first flag register that holds the first flag information indicating whether the flag is valid or invalid and provides the second memory access circuit with the first flag information;
Of the second address and the second access address given from the second memory access circuit match, and the second flag information given from the second memory access circuit causes the second flag A first comparison / determination unit suspends access to the first port when the access address is considered to be valid.

The second memory access circuit is the second memory access circuit.
Second access address register for holding the second access address to be output to the port and giving it to the first memory access circuit, and the second flag information indicating whether the second access address is valid or invalid. And a second flag register which holds the value and gives it to the first memory access circuit, and a comparison result of the second access address and the first access address given from the first memory access circuit. And secondly stopping access to the second port when the first access address is determined to be valid by the first flag information provided from the first memory access circuit.
And a comparison / determination unit.

According to the first invention, since the memory access circuit is configured as described above, the following operation is performed. For example, when the first memory access circuit accesses address A of the dual port memory, if the access address of address A is output to the first port, the address A is held in the first address register and Flag information indicating that the flag is valid is held in the flag register. The contents of the first address register and the flag register are given to the comparison / determination unit of the second memory access circuit. Similarly, the contents of the second address register and the flag register are given from the second memory access circuit to the comparison / determination unit of the first memory access circuit. Then, the contents of the first and second address registers are compared in the comparison / determination unit of the first memory access circuit. If the contents of the first and second address registers match and the flag information of the second memory access circuit is valid, the first memory access circuit stops the access to the address A of the first port. To be done.

In the second invention, the first and second memory access circuits for accessing the dual port memory are configured as follows. The first memory access circuit is configured to provide a first flag output section for providing the second memory access circuit with first flag information indicating whether the first access address output to the first port is valid or invalid; The second access address given by the second memory access circuit matches the comparison result of the first access address and the second access address output from the second memory access circuit to the second port. And a first comparison / determination unit that suspends access to the first port when the second access address is determined to be valid by the flag information.

The second memory access circuit is the second memory access circuit.
A second flag output unit for providing the first memory access circuit with the second flag information indicating whether the second access address to be output to the port is valid or invalid, the second access address and the first Of the first access address output from the memory access circuit of the first memory access circuit to the first port, and the first flag information provided from the first memory access circuit causes the first flag information to be output.
When the access address of is
And a second comparison / determination unit that suspends access to the second port.

According to the second invention, the following operation is performed. For example, when the first memory access circuit accesses address A of the dual port memory, when the access address of address A is output to the first port, the contents of this access address are compared and determined by the comparison / determination unit of the second memory access circuit. Is output to. Further, flag information indicating that the access address is valid is output from the flag output unit to the comparison / determination unit of the second memory access circuit.

Similarly, the comparison address of the first memory access circuit is given the access address and flag information from the second memory access circuit. Then, in the comparison / determination unit of the first memory access circuit,
And the second access address are compared. If the first and second access addresses match and the flag information of the second memory access circuit is valid, the first memory access circuit stops the access to the address A of the first port. .

[0021]

1 is a schematic configuration diagram of a system including a memory access circuit showing an embodiment of the present invention. This system includes a first functional block (eg,
CPU) 50 and a second functional block (eg CC
P) 60 and a dual port memory (for example, dual port RAM) 10 accessed by the CPU 50 and the CCP 60. The CPU 50 controls the entire system, and the CCP 60 performs data communication with another system or the like via a communication line (not shown). In addition, the dual port RAM 10 stores, for example, data to be transmitted from the CPU 50 to another system in C
It is used as a buffer memory for passing the data to the CP 60 or the data received by the CCP 60 from another system to the CPU 50.

The dual port RAM 10 has, for example, 25
A storage unit 11 having a storage area of 6 words × 8 bits;
Two ports 1 for accessing this storage unit 11
It is composed of 2 and 13. Each of the ports 12 and 13 can write and read data independently of the storage unit 11. C
PU50 and CCP60 are dual port R respectively
A memory access circuit 50A for connecting to the AM10,
It has 60A. Memory access circuits 50A, 60
A has the same configuration. For example, the memory access circuit 50A has an access address register 51 which stores an access address to the dual port RAM 10, a flag register 52 which shows flag information indicating whether or not the dual port RAM 10 is currently accessed, and an access to the dual port RAM 10. The comparison / determination unit 53 determines whether or not to perform. Memory access circuit 50A and dual port RAM 10 port 1
The two are connected by an 8-bit address bus 54, an 8-bit data bus 55, and a several-bit control bus 56.

Similarly, the memory access circuit 60A is composed of an access address register 61, a flag register 62, and a comparison / decision unit 63, and has an 8-bit address bus 64, an 8-bit data bus 65, and a several-bit control bus. Port 1 of dual port RAM 10 via 66
Connected to 3. The contents of the access address register 51 and the flag register 52 of the memory access circuit 50A are supplied to the comparison / determination unit 63 of the memory access circuit 60A via the signal lines 57 and 58, respectively. The comparison / determination unit 63 detects a match between the contents of the access address register 51 and the value of the address bus 64, and a match detection unit 63a that matches these values and the dual port RAM 10 according to the flag information of the flag register 52.
When it is shown that access to
The dual port RAM 10 is composed of a logical product gate (hereinafter referred to as "AND") 63b which outputs a wait signal WA for delaying access.

Similarly, the contents of the access address register 61 and the flag register 62 of the memory access circuit 60A are supplied to the comparison / determination unit 53 of the memory access circuit 50A via signal lines 67 and 68, respectively. The comparison determination unit 53 ANDs with the coincidence detection unit 53a.
53b, the contents of the access address register 61 and the value of the address bus 54 match, and the dual port RAM 10 is configured by the flag information of the flag register 62.
When it is shown that access to
A wait signal WA for delaying access on the memory access circuit 50A side is output.

Next, the operation will be described. For example, CPU50
When accessing the address A of the dual port RAM 10, the dual port RAM 10 is stored in the flag register 52.
The address signal of address A is output to the address bus 54 while "1" indicating that the access is being performed is set. The address signal output to the address bus 54 is stored in the access address register 51. Then, from the memory access circuit 50A to the port 12
Read / write access to the storage unit 11 of the dual port RAM 10 is performed via the. When the access to the dual port RAM 10 is completed, the CPU 50 sets “0” in the flag register 52, which indicates that the dual port RAM 10 is not accessed. On the other hand, C
When the CP 60 accesses the same address A of the dual port RAM 10, similarly, "1" indicating that the dual port RAM 10 is being accessed is set in the flag register 62, and A is set to the address bus 64. The address signal of the address is output. The address signal output to the address bus 64 is stored in the access address register 61.

An address signal of address A is given from the access address register 51 on the CPU 50 side via the signal line 57 to the comparison / determination unit 63, and the flag register 52 is further supplied.
“1” is given from the via the signal line 58. Here, when the address signal of the address A is given from the address bus 64 to the comparison / determination unit 63, the comparison / determination unit 63 outputs the wait signal WA to the CCP 60. As a result, in the CCP 60, the access to the address A of the dual port RAM 10 is postponed until the wait signal WA is stopped. On the contrary, when the CCP 60 is accessing the address A of the dual port RAM 10, the C
When the PU 50 tries to access the same address A in the dual port RAM 10, the comparison / determination unit 53 sends a CP
The weight signal WA is output to U50. As a result, in the CPU 50, the access to the address A of the dual port RAM 10 is postponed until the wait signal WA is stopped.

As described above, each of the memory access circuits 50A and 60A of this embodiment is a dual port RAM.
Comparing the address signals given to the two ports 12 and 13 of 10 with comparison / decision units 53 and 63 for outputting the wait signal WA to the port to which the same address signal is output later. ing. With this, without increasing the processing time with a simple circuit,
There is an advantage that the simultaneous access to the same address of the dual port RAM 10 is prohibited and the validity of the data can be maintained.

The present invention is not limited to the above embodiment, and various modifications can be made. Examples of this modification include the following (a) to (e). (A) The storage capacity (the number of words and the number of bits) of the dual port RAM 10 is not limited to the illustrated one, and the same can be applied to any storage capacity. (B) Without providing the access address registers 51 and 61, the address buses 54 and 64 are directly connected to the signal lines 57 and 67, and the address signal being accessed is compared and determined by the comparison / determination unit 63.
You may make it give to 53.

(C) Instead of the flag registers 52 and 62, a flag output section composed of a logic circuit for outputting flag information indicating whether the access address is valid or invalid may be provided. This eliminates the need for a latch circuit for holding the valid / invalid flag information, thus simplifying the circuit. (D) The address signals to be compared in the comparison / determination units 53 and 63 are not limited to 8 bits. Further, the lower bits may be ignored and only the upper bits may be compared without making all the bits of the address signal to be compared. As a result, the time required to be determined as competition increases, but the circuit can be further simplified. (E) Ports 12 and 13 of the dual port RAM 10
The functional blocks connected to CPU50 and CCP6 are
The memory access circuits 50A, 6
Any functional block can be connected as long as it has 0A.

[0030]

As described in detail above, according to the first invention, access address registers for holding the access addresses output to the first and second ports of the dual port memory, and these access addresses. When the contents of the registers are compared with each other and the access addresses are valid and coincident with each other, a comparison / determination unit is provided to stop the access to the port that outputs the same access address later. As a result, there is an effect that the simultaneous access to the same address of the dual port memory can be prohibited and the validity of the data can be maintained without increasing the processing time with a simple circuit.

According to the second invention, the access address register of the first invention is deleted so that the access addresses output to the address buses of the first and second ports are directly compared. This makes it possible to obtain the same effect as that of the first aspect of the invention with a simpler circuit.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a system including a memory access circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a system using a conventional dual port RAM.

[Explanation of symbols]

10 dual port RAM 11 Memory 12, 13 ports 50 CPU 50A, 60A memory access circuit 51, 61 access address register 52,62 Flag register 53, 63 Comparison judgment unit 54, 64 address bus 55,65 data bus 60 CCP

Claims (2)

(57) [Claims] 1. A first port and a second port for accessing a dual port memory capable of independently performing read / write access to arbitrary addresses from a first port and a second port with respect to a common storage area. In the first and second memory access circuits respectively connected to the first memory access circuit, the first memory access circuit holds the first access address to be output to the first port, and stores the first access address in the second memory access circuit. A first access address register for giving; a first flag register for holding first flag information indicating whether the first access address is valid or invalid and giving it to the second memory access circuit; The result of comparison between the access address and the second access address given by the second memory access circuit is the same, and the second memory address is A second comparison information determination unit that suspends access to the first port when the second access address is valid according to the second flag information provided from the access circuit. The second memory access circuit has a second access address register that holds the second access address to be output to the second port and gives the second memory access circuit to the first memory access circuit. The second, valid or invalid
Comparing the second access address and the first access address given from the first memory access circuit with the second flag register holding the flag information of the second memory and giving it to the first memory access circuit. The access to the second port is stopped when the results match and the first access address is determined to be valid by the first flag information provided from the first memory access circuit. And a second comparison / determination unit for controlling the memory access circuit. 2. A first port and a second port for accessing a dual port memory in which read / write access can be independently made to an arbitrary address from a first port and a second port with respect to a common storage area. In the first and second memory access circuits respectively connected to the first memory access circuit, the first memory access circuit outputs first flag information indicating whether the first access address output to the first port is valid or invalid. A first flag output section to be given to the second memory access circuit, and a comparison result of the first access address and a second access address outputted from the second memory access circuit to the second port. And the second access address is valid according to the second flag information given from the second memory access circuit. And a first comparison / determination unit that suspends access to the first port, wherein the second memory access circuit determines whether the second access address output to the second port is valid or invalid. A second flag output section for giving the second flag information to the first memory access circuit; the second access address and the first flag output from the first memory access circuit to the first port; If the result of comparison with the first access address is the same, and the first access address is valid according to the first flag information provided from the first memory access circuit, the first access address is valid. A memory access circuit comprising: a second comparison / determination unit that suspends access to the second port.