JPS6049943B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to a data processing device having means for specifying reading or writing of a plurality of pieces of data in a memory using the same address data.

In recent years, with the expansion of data processing functions, the amount of reserved memory has also tended to increase, but memory and central processing units (CPUs)
Alternatively, a common method is to use a common bus for data transfer with various peripheral devices. This bus is used to transfer data with a bit length of 4 bits | 8 bits, etc., but when addressing a particularly large capacity memory, this memory (read-only memory: ROM
, readable/writable memory (including RAM) into multiple chips or multiple blocks within the same chip, and use the same address data for each chip or block to create programs or software. We are trying to simplify the process.

Of course, each memory chip and memory block header are commonly connected to the same address and data bus, so when accessing memory with the same address data, only one Only one block can be selected. Conventionally, in such an apparatus, the configuration shown in FIG. 1 is known as selection means.

That is, the data processing device includes RMM15, 16 and ROMI.
Each of these memory blocks has the same address value as the other and is connected to the address bus 9 and data bus 8 of the CPUI. Further, the upper bits of the addresses to these memories are decoded by the decoder 2 and outputted as an address decode signal 10, which is used to control the opening and closing of the AND gates 23-26. On the other hand, there is a data latch 3 and its decoder 4 as means for selecting one of these four memory blocks, and the CPU
Before addressing these memory blocks, it is necessary to write instruction data to the data latch 3 for specifying which memory block to select. The instruction data written into the data latch 3 under the output of the latch control signal 7 is decoded by the decoder 4 and
One block selection signal 11-14 is generated corresponding to one memory block. This block selection signal 11~
14 is. Decoded signal 1 by AND guts 23 to 26
A logical operation is performed with 0, resulting in memory selection signals 19 to 22, and only one out of RAM15, l6 and ROM17, l8
Select one memory block. Here ROM17,l
The signals 19 and 20 for selecting 8 are further connected to AND gates 23'' and 23'' by the read control signal 6 output from the CPU1.
24' to select ROMs 17 and 18. In this way, the data processing device selects only one memory block among the plurality of memory blocks in the same memory block, specifies the address within the block using the lower address bits on the address bus 9, and sequentially performs a read operation. Execute. On the other hand, R. Write operations to AMl5 and l6 are performed by the CPU.
This is carried out when the write control signal 5 is output from 1. However, when using the above data processing device, it is possible to select one memory block with one address signal and perform a read or write operation on that memory block, but it is possible to perform a read or write operation on that memory block. Since the same address is used, it is impossible to address another memory block as necessary during program processing using program data.

For example, while a program written in ROM17 is being executed, RAM15 or 1 at the same address is
6, it had the disadvantage that a write operation could not be performed. Therefore, when such a need arises, the CPU
temporarily suspends selection of the currently addressed memory block, writes instruction data to select another memory block to latch 3, selects the memory block (RAM) to be written, and writes the desired data. After writing to this RAM, it was necessary to go through the previously described procedure of selecting the previous memory block again. For this reason, the processing time becomes unnecessarily long and the processing program becomes complicated. The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a data processing device that shortens processing time and has a simplified processing program.

The present invention provides a plurality of memory blocks to which the same address is assigned, a data processing section that accesses the plurality of memory blocks, a common bus connecting the data processing section and the plurality of memory blocks, and a common bus that connects the plurality of memory blocks to the plurality of memory blocks. a first means for selecting a part of the blocks, a second means for selecting another part of the plurality of memory blocks, and a memory block selected by the first means is in a selected state. means for prohibiting data from being read from the common bus to the common bus while maintaining the same state, and means for writing data on the common bus to the memory block selected by the second means in the read-prohibited state. It is characterized by having the following. An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a functional block diagram of a data processing device showing one embodiment of the present invention.

RAM configured by the same address in each block
15O, 16O and ROMs 17O, 18O are connected to an address bus 90 from the CPU 1OO having an arithmetic processing function, and read data buses 34 to 37 that output read data from each memory are connected to the CPU OO via data buffers 42 to 45. It is connected to the connected data bus 80.

Further, the address bits of the addresses for these memories are decoded by a decoder 200 and an address decode signal 10 is generated.
00 for each memory block. Select all. On the other hand, there is a data latch 300 and a decoder 400 connected thereto as means for selecting one of these memory groups, and the CPU 100 determines which memory block to perform a read operation on before accessing these memories. It is necessary to write data to the data latch 300 for selecting whether the The selection data written in the data latch 300 is decoded by the decoder 400 and sent to the AND gates 38-4 via the selection signal lines 110-140.
1 is input. these. The other input terminals of the AND gates 38 to 41 are connected to the read control signal line 6 from the CPU1OO.
0 is connected, and the AND gates 38 to 41 are controlled to open or close according to the input of this read control signal. This A
Each output of the NP gates 38 to 41 is connected to a data buffer 42 to
A signal line 110 that decodes and outputs the selected data during the period in which the read control signal is output.
A signal for closing the data buffer and electrically connecting the memory and the data bus is output from the AND gate to which the selection signal sent through one of the lines 140 is input. As a result, RAM l5O, l6O and ROM l7O, l8
Only one selected memory block in O is allowed to output data to data bus 80 when read. Furthermore, there is a data latch 33 as a control means for writing data to the RAMs 15O to 160, which is controlled by the CPU like the data latch 300 for memory block selection.
The lOO data bus 80, address 90, and latch control signal 70 are input, and a RAM selection signal is output to the signal lines 29 and 30 in accordance with the data written in the data latch 33. In other words, CPUlOO writes R before writing data to random access memory (RAMl5O, l6o).
It is necessary to write data for ArlV4 selection into the data latch 33. The selection data written to the data latch 33 is logically operated with the write control signal supplied via the write control signal line 50 from the CPU 1OO connected to the single input terminals of the N1 gates 27 and 28, and then stored in the RAM.
Connected to the write control terminals of l5O and l6O. Further R
．． The write data bus for AMl5O and l6O is the CPU.
The RAM block selected by the RAM selection data set in the data latch 33 is connected to the data bus 80 of lOO, and the data write operation to the RAM is performed when the RAM block selected by the RAM selection data set in the data latch 33 is connected to the data bus 80. Write data is input from 80 and written into the memory. According to the data processing device of this embodiment, when the CPU 100 selects the ROM block 170, reads data, and executes a predetermined program process based on the data, the CPU 100 selects the ROM block 170, reads data, and executes a predetermined program process based on the data.
Selection data for selecting the data is stored in the data latch 300.

The selection data stored in the data latch 300 is decoded by the decoder 400 and sent to the ROM latch via the selection signal line 120.
AND gate 40 controlling 7O data buffer 44
A selection signal is input to. On the other hand, CPUlOO outputs a read control signal (synchronized within the CPU and output in the data read cycle) using the signal line 60,
Data buffer 44 between the ND gate 40 and the ROM170 data read bus 36 and the common data bus 80
, the data stored in the address in the ROM 17O specified by the lower address bits input from the address bus 90 is read out, and program processing is executed based on the data. During this program processing period, for example, R
When it becomes necessary to write data to AM15O or 160, CPU10 stores selection data for selecting RAM15O, for example, in data latch 33, and sends a selection signal to AND gate 28 via signal line 30, which is its output. Furthermore, CPUlOO outputs a data write control signal to the signal line 50 at the write timing, and outputs a write control signal to select RAMl5O from the AND gate 28 via the signal line 32. At this time, R. AMl5
Since the data read buffer 42 of O is open and the data read bus 34 and the data bus 80 are electrically separated, the RAM 15O outputs the data on the data bus to the current address bus 90 via the bus 51. RAM15, which is the same address as the address to ROM17O
Write to the address in O. When this write operation is completed, the CPU 100 turns off the output of the write control signal, so that the program data can be read out from the ROM 170 and the processing can be continued. still,
In the structure of this embodiment, RAM l5O, l6O are read data buses 34, 35 and write data buses 51, 5.
2, both of which are connected to a common bus 80, but when reading data, the write bus 51,
Writing of undesired data into the RAM via the CPU 52 can be avoided unless a write control signal is output from the CPU 100. As described above, according to this embodiment, when writing data at the same address in another memory while reading data by specifying ROM 17O and executing a program process, the data latch 33 is simply
By simply using the , data can be written without the need to switch the memory block selection, resulting in significant effects that could not be obtained with conventional devices, such as a significant reduction in program processing time and the amount of programming required. can be achieved. Each memory block may be formed by dividing a memory area formed on the same chip together with the CPU into a plurality of blocks and allocating the same address to each block, or each memory block may be formed from an independent chip. The number of blocks can be set arbitrarily.

Furthermore, when the memory capacity is relatively small, the upper bit address decoder 200 may be omitted and the read control signal from the CPU1OO may be used instead. Furthermore, the data buffer connecting the memory and the bus may be simply a gate means or a register. Furthermore, the address used when writing to the RAM can be within a range that does not exceed the address in the selected ROM.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional data processing apparatus, and FIG. 2 is a block diagram of an embodiment of the present invention. 1,100...CPU12,2OO...Address decoder, 3,33,300...Data latch, 4,4
00...Decoder, 5,50...Write control signal line, 6,60...Read control signal line, 7,70...Latch control signal line, 8,80...Data bus, 9, 90
...Address bus, 10,1000...Address decode signal, 11-14,110-140...Memory block select signal, 19-22...Memory selection signal, 29,30...Write select signal , 42-45
... Read data buffer, 38 to 41, 27, 28
...AND gate, 23~26,235,24''...
・AND gate, 15, 16, 150, 160...R,
AMll7, l8, l7O, l8O...ROM.

Claims (1)

[Claims] 1 A plurality of memory blocks to which the same address is assigned, a data processing section that accesses these plurality of memory blocks, a common bus that connects the data processing section and the plurality of memory blocks, and a common bus that connects the plurality of memory blocks. a first means for selecting a part of the plurality of memory blocks; a second means for selecting the other of the plurality of memory blocks; and a memory block selected by the first means is maintained in a selected state. and means for writing data on the common bus into the memory block selected by the second means in the read-prohibited state. A data processing device characterized by: