JPS6284349A - Memory control device - Google Patents

Abstract

PURPOSE:To reduce a store buffer to the minimum number of gates by making the bit width of a main memory address fewer than data by several bits by logic physical conversion. CONSTITUTION:Access from a CPU 100 to a main memory 300 and an IO device 400 is wholly made through a memory control device 200. It is judged by a circuit 270 whether the access from the CPU 100 is to the main memory 300 or to the IO device 400. In the case of access to the main memory 300, an operation command is give to a main memory access controlling circuit 230 and a store buffer 260. The command to the store buffer is effective only in the case of write access. In the case where access from the CPU 100 is to the IO device, a command is given to an IO access control circuit 240 through a line 214.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a store buffer in a memory-based @device, and in particular to a store buffer that is effective when the device is configured with elements such as gate arrays that have a limited amount of hardware. Regarding.

[Background of the invention]

Regarding the store buffer for speeding up write access from the CPU, for example, Japanese Patent Application Laid-Open No. 56-1999 describes how to quickly flush out data in the store buffer or how to avoid storing unnecessary data. 54558
The device has been devised as seen in the publication. but,
Up until now, no effort has been made from the perspective of the amount of hardware that makes up the store buffer.

[Purpose of the invention]

An object of the present invention is to realize a store buffer circuit with a minimum number of gates.

[Summary of the invention]

A store buffer is composed of one or more pairs of data and an address for storing the data. Addresses in 10 accesses are generally expressed with the same bit width as the data to ensure a wide open area, but main memory addresses are
Generally, the bit width is several bits less than the data.

The present invention focuses on this point and makes it possible to realize a store buffer with a minimum number of gates.

[Embodiments of the invention]

Figure 1 shows a diagram of the system configuration. 100 is CP[J,
2 (10 is a memory control device), and access from the CPU to the main memory 300 and the 10 devices 400 is performed through all the memory distribution devices.

FIG. 2 is a diagram showing the internal configuration of the memory control device. 2
20, 230, and 240 are a CPU interface circuit, a main memory access bypass circuit, and an IO access control circuit, respectively. 250 is an address conversion circuit for converting a logical address output from the CPU into a physical address, and 260 is a store buffer that holds write data to the main memory together with the address.

201, 202, 203 are the CPU and memory ff1l respectively
1 represents the address/data/system No. 11i bus between devices. Further, 204 to 206 and 207 to 209 indicate addresses, data, and data between the main memory and the IO device, respectively.
21 represents a collateral signal bus, and 210 to 212 represent address, data, and control signal paths within the memory control device.

270 is a circuit that determines whether the access from the CPU is to the main memory or to l09fit; if the access is to the main memory IJK, it is connected to the main memory access control circuit via 213; ,
Give operation commands to the store buffer. However, the @create command for the store buffer is valid only for write access.

Further, if the access from the CPU is to the 0 device, a command is given to the IO access control circuit via 214.

In this way, store it in the store buffer.

It can be only data and addresses for main memory, and addresses are logical addresses handled within the CPU, i.e.,
Since the bit width is narrower than the address used for IO access, the store buffer can be configured with less hardware.

FIG. 3 shows an example using a logical address area as an example for determining whether an access from CP[J is an access to the main memory or an access to the 0 device. In this example, the address width is 32 bits, and the address area from $00000000 to $7FFFFFFFF is the main memory area.

The IO area is $80000000 to 8F'FFFFFFFF. However, $ represents a hexadecimal number.

Correspondingly, 270 in FIG. 2 determines whether it is a main memory access or an IO access.
In this embodiment, only the most significant bit) is used.

Figure 4 shows another example of how to determine whether an access from the CPU is to main memory or to an IO device.
An example using a 1tl signal was shown.

In this case, the main memory and ■0 each have 4 GB (
If the CPU address is 32 pits wide), it can have a logical space of 32 bits.

In this case, the control 11 signal bus is selected as the input at 270 in FIG.

〔Effect of the invention〕

32-bit 1-chip CPU, which is currently being widely used.
In this case, the physical address is generally chosen in the range of 22 to 26 bits. This means that if you store a physical address in the store buffer, it will be 6 to 1 times more expensive than if you store a logical address.
This shows that 0 bits can also be short. - If 4 gates are required to configure a 7-bit lip-flop, the reduction will be 24 to 40 gates per entry in the store buffer. For example, assuming that an entry is prepared as a store buffer, 192 to: This is a reduction of 20 kg.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a system according to an embodiment of the present invention, FIG. 2 is a system diagram of a memory control device implementing the present invention, and FIGS. 3 and 4 show main memory access and IO access. It is a figure which shows the example of a means for separating. 100...CP[J, 200...Memory control device (
MCU), 300... Main memory, 400... Engineering device.

Claims (1)

[Claims] 1. An address conversion circuit that converts a logical address output from a processing device into a physical address, a store buffer and a main memory access control circuit that temporarily store data output from the processing device together with the physical address to be stored. , a memory control device comprising an IO access control circuit, comprising means for determining whether the output data is data for the main memory or data for the IO, and means for storing only data for the main memory in the store buffer. A memory control device characterized by: