JPH04372029A - Storage device - Google Patents

Abstract

PURPOSE:To make the storage device economical and efficient by setting the word line of a mounted storage module in advance and controlling the memory address so that the mounted physical memory space of each storage module continues based on this. CONSTITUTION:A set circuit (h) holds the set value of the word line of storage modules (d) and (e) composed of the mounted DRAM modules. A control circuit (g) controls the memory address of the modules (d) and (e) so that the mounted physical memory space of the storage modules (d) and (e) continues based on the set value of the number of words held in the set circuit (h). Here is the case where the structure of the modules (d) and (e) are clear in advance. However, when the socket mounting DRAM module is used, a simple exchange can be performed so that the set value may not be determined in advance. Thus, a means checking the structure of the mounting DRAM modules and setting the obtained structure to the set circuit (h) is provided, if possible.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device using a plurality of storage modules.

0002

[Prior Art] Currently, dynamic RAM (random RAM)
Access memory) (hereinafter referred to as DRAM) mounted on a small substrate called a DRAM module is generally used for reasons such as mounting efficiency and expansion. D.R.
There are many types of AM modules depending on word configuration, capacity, etc. Figure 11 shows a typical DRAM.
Indicates the type of module. In other words, the number of words that can be memorized (
As a W (word) configuration indicating depth), 256K, 51
There are 2K, 1M, and 2M, and there are 8, 9, 32, 36, and 40 bits as bit configurations indicating word width. A memory device using such a DRAM module is constructed.

FIG. 12 shows the memory device. The device shown in the figure consists of a decoding circuit a, a multiplexer b, a timing control circuit c, DRAM modules d and e, and a data buffer f. The decoding circuit a receives a signal 5 indicating memory access and a signal 1 indicating whether or not the address is for this memory device.
This is a circuit that outputs a signal 7 indicating this in the case of an address to this memory device, and a multiplexer b
is a signal 2 indicating a row address or a signal 3 indicating a column address according to a selection signal 8 from a timing control circuit c.
This is a selector switch that selects the output. Further, the timing control circuit c is a circuit that receives a selection signal 4 of the DRAM modules d and e, a signal 6 indicating read/write, and an output signal 7 of the decoding circuit a, and outputs a timing control signal to be described later. Further, the DRAM modules d and e are configured to have 1 MW×8 bits, and the data buffer f is a circuit that buffers the storage contents of the DRAM modules d and e. .

Signals 1, 2, 3, and 4 are address buses to which the present memory device is connected, respectively; signal 1 is the decode circuit a, signal 2 is the input A of the multiplexer b, and signal 3 is the input of the multiplexer b. B, signal 4 is connected to timing control circuit c. Signal 5 indicates memory access and is connected to decode circuit a. Signal 6 is a signal indicating read access or write access, and is connected to timing control circuit c. Signal 7 is an output signal of decoding circuit a, and is connected to timing control circuit c. Signal 8 is a selection signal output from timing control circuit c and is connected to multiplexer b. The signal 10 is a RAS (row address strobe) for the memory.
This is a row address strobe (row address strobe) signal and is connected to DRAM modules d and e. Also, signals 11, 1
2 is CAS (column addr
ess strobe (column address strobe) signal, which is connected to DRAM modules d and e, respectively. Signal 9 is the output signal of multiplexer b and is connected to the address inputs of DRAM modules d and e. Further, a signal 16 is a data bus for DRAM modules d and e, and is connected via a data buffer f to a data bus 17 to which this memory device is connected. Further, signals 14 and 15 are an enable signal and a direction control signal for the data buffer f, and are outputted from the timing control circuit c and connected to the data buffer f.

Next, the operation of the memory device having the above configuration will be explained. FIG. 13 is a diagram showing the timing of the memory device. First, the decoding circuit a detects that the signal 5 is "0",
That is, when it is a memory access and signal 1 has a value indicating the memory space of this memory device, signal 7 indicating that this memory device is being accessed is set to "0" and this is sent to timing control circuit c. Notice. timing control circuit c
When the signal 7 becomes "0", it sets the enable signal 14 of the data buffer f to "0" and outputs the direction control signal 15 of the data buffer f according to the read/write signal 6. In addition, the timing control circuit c outputs a write signal 13 to the DRAM modules d and e in accordance with the read/write signal 6, and further sets the selection signal 8 to "0" to the multiplexer b, so that the DRAM module d , e as a row address, and then inverts the RAS signal 10 to "0". Then, to give the column address, set signal 8 to "1" and set signal 3 to DR.
AM modules d and e.

Then, it is determined based on the signal 4 whether DRAM module d or e is to be accessed, and when accessing DRAM module d, the inverted CAS0 signal 11 is set to "0" and DRAM module e is accessed. In this case, the inverted CAS1 signal 12 is set to "0" to access the DRAM modules d and e. Then, all the control signals 8, 10, 11, 12, 13, 14, and 15 output from the timing control circuit c are returned to predetermined values, and the series of accesses is completed.

[0007]

[Problems to be Solved by the Invention] However, the memory device with the above configuration does not have the same configuration as the DRAM module (1) shown in the example.
If you try to use a module with a configuration other than MW x 8 bits, various inconveniences will occur. For example, if a 256KW x 8-bit DRAM module is used in the above configuration, the installed physical memory space will be discontinuous.

FIG. 14 shows the state. That is, 1MW×
When using a 256KW x 8-bit DRAM module with an 8-bit configuration, the DR with a 256 x 8-bit configuration
The memory address of the AM module is 000000H
From 03FFFFH and from 100000H to 13F
The physical memory space becomes discontinuous, such as up to FFFH. Therefore, even if a capacity of 512 Kbytes is sufficient, there is an inconvenience that 1 MW x 8 bits (1 Mbyte) must be implemented. Also, this applies not only to 256x8 bits, but also to any D
A similar problem arises depending on the combination of RAM modules. The present invention was made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an economical and efficient memory device.

[0009]

[Means for Solving the Problems] A first aspect of the memory device of the present invention is to set a setting value for the number of storable words of each installed memory module in a memory device using a plurality of memory modules. A setting circuit to hold,
The device is characterized by comprising a control circuit that controls the memory address of each of the storage modules so that the mounted physical memory spaces of the plurality of storage modules are continuous based on the setting value held by the setting circuit. be. Further, a second invention according to the first invention includes setting means for checking the number of words that can be stored in each memory module to be installed and setting the obtained number of words for each memory module in the setting circuit. It is characterized by this.

0010

In the memory device of the present invention, in which a plurality of storage modules are used, the setting circuit h holds a setting value for the number of words of the installed storage modules d and e. The control circuit g controls the memory address of each storage module so that the installed physical memory spaces of the plurality of storage modules are continuous based on the set value of the number of words held in the setting circuit. Therefore, an economical and highly efficient memory device can be obtained.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a memory device of the present invention. The device in the figure includes a control circuit g, a setting circuit h
, multiplexer b, storage modules d, e, and data buffers f, i, where the storage modules d, e are DRA
It is composed of M modules. The control circuit g is a circuit consisting of a timing control section j and a decoding control section k, which will be described later. Further, the setting circuit h is a register for setting the configuration of the DRAM modules d and e. The multiplexer b is a circuit that receives a signal 100 indicating a row address and a column address, and switches between the row address and column address in response to a selection signal 103 output from the control circuit g. DRAM module d
, e uses a 4MW×8 bit configuration. In addition, the data buffer f is connected to the DRAM module d as before.
, e, and the data buffer i is a buffer that buffers the data of the setting circuit h.

Signal 100 is an address bus to which the memory device of this embodiment is connected, and of the 24-bit address A23-0, 6 bits A23 to A18 are connected to control circuit g, and A21, A19, A17-A9 1
1 bit goes to input A of multiplexer b, and A20
, A18, 11 bits of A8 to A0 are multiplexer b
is connected to input B of the Signal 101 is a signal indicating memory access, and is connected to control circuit g. Signal 102 is a signal indicating read or write, and is connected to control circuit g, setting circuit h, and data buffer i. Signal 103 is a selection signal for multiplexer b, which is output from control circuit g and input to multiplexer b. Signal 104 is a multiplexed signal, and is a multiplexed signal for DRAM modules d and e.
connected to the address terminal of The signal 105 is a RAS signal for the memory, and is output from the control circuit g.
Connected to DRAM modules d and e. signal 106
and 107 is a CAS signal for the memory,
are output from the control circuit g, and are output from the DRAM modules d,
connected to e.

Signal 108 is a write signal for the memory, and is output from control circuit g and connected to DRAM modules d and e. Signal 109 and Signal 110
are the enable signal and direction control signal of data buffer f. A signal 111 is a data bus for DRAM modules d and e, and is connected via a data buffer f to a data bus 112 to which the memory device of this embodiment is connected. Signal 113 is a selection signal for setting circuit h, which is an output from another decoding circuit, and is connected to setting circuit h as well as to the enable terminal of data buffer i. Signal 115 is a data bus for setting a value in setting circuit h, and is connected to data bus 112 via data buffer i.

FIG. 2 shows the correspondence between the configuration of the DRAM module and the set values of the registers. Furthermore, in this example,
256KW x 8 bits, 1MW x 8 bits, 4MW x 8
It is assumed that up to two DRAM modules with three types of bit configurations can be used. That is, b1 and b0 of the setting circuit h indicate the setting values of the DRAM module d, b3 and b2 indicate the setting values of the DRAM module e,
The configuration is such that these set values are output as a signal 114 to the control circuit g. Also, b4 of setting circuit h ~
b7 is set to invalid. Further, it is assumed that the settings of the setting circuit h are performed from a higher-level processor (such as a CPU).

FIG. 3 shows the internal configuration of control circuit g. The control circuit g consists of a timing control section j and a decode control section k, a signal 101 is connected to the timing control section j and the decode control section k, and a signal 102 is connected to the timing control section j. Out of 100 signals, A23~
The six signals of A18 and signal 114 are connected to decode control section k. Decode control unit output signal 122
is connected to the timing control section j, and the signal 123 (R
AS signal decode signal), 124 (CAS signal decode signal for DRAM module d), 125
(Decoded signals of CAS signals for DRAM module e) are input to OR gates l, m, and n, respectively. The output 120 (timing signal of the RAS signal) of the timing control section j is connected to the OR gate l, and the output 121 (CA
The timing signal of the S signal) is input to OR gates m and n. The outputs of OR gates l, m, and n become signals 105, 106, and 107, respectively. Furthermore, the signals 103 , 108 , 109 , and 110 are output from the timing control section j, respectively. Note that the decoding control unit k receives input signals 100, 101, 114, for example.
address, output signals 122, 123, 124
, 125 as data, they can be constructed using ROM (read-only memory) or the like, or they can be constructed simply using logic gates.

Next, the operation of the memory device having the above configuration will be explained. FIG. 4 is a diagram showing the timing of a portion centered on the control circuit g. Further, FIG. 5 is a diagram showing truth values of the decoding control section k. First, the decoding control section k
are the signals 101 and D indicating memory access.
It is determined whether this access is a memory access of this memory device from the signal 114 of the configuration setting value of RAM module d, e and the address signal 100, and if it is an access to this memory device, the selection signal 122 is set to "
0'' and notifies this to the timing control unit j. The timing control section j starts operating when the signal 122 becomes "0" and outputs each signal at the timing shown in FIG.

That is, initially, the selection signal 103 is "0".
Therefore, the signal 104 is used as the row address, A2
1, A19, and A17-9, and after that, when the selection signal 103 becomes "1", the signal 104
are column addresses, A20, A18, A8~0
address. Further, the logic of the signal 120 output from the timing control section j and the output Q1 (signal 123) of the decoding control section k is taken by the OR gate l, and the inversion RA
The S signal becomes 105. Furthermore, the signal 121, the outputs Q2 (signal 124) and Q3 (signal 1) of the decoding control section k
25) is logically taken by the OR gates m and n, respectively, and the inverted CAS0 signal 10 to the DRAM modules d and e is
6 and an inverted CAS1 signal 107. here,
The decoding control unit k receives its input signals 100 and 114.
Accordingly, the output 12 is set so that the DRAM modules d and e have a predetermined memory configuration and their memory addresses are continuous.
3, 124, and 125 are decoded.

FIG. 6 is an explanatory diagram showing the memory configuration. For example, DRAM module d is 256KW x 8
When the DRAM module e is set as a 4MW x 8 bit configuration, as shown in the truth value of FIG.
The 56K space is used for the signal 12 to output the inverted RAS signal 105 for access of the DRAM module d.
3 is set to "0", and the signal 124 is set to "0" in order to output the inverted CAS0 signal 106. Next, address 04
The 4M space from 0000H to 43FFFFH is DRA
Since the access is to M module e, the inverted RAS signal is 0.
The signal 123 for outputting 15 is set to "0", inverted CA
The signal 125 for outputting the S1 signal 107 is set to “0”.
”. In addition, even in other memory configurations, the decode control unit k outputs 12 outputs so that the memory addresses of the DRAM modules d and e are continuous based on the setting value of the setting circuit h.
By decoding 3, 124, and 125 and controlling each DRAM module d and e, continuous memory addresses can be obtained as in the above case.

In the above embodiment, the configuration of the DRAM modules d and e to be used is known in advance, but depending on the device, there may be cases where it is not known which configuration of DRAM modules will be installed and in what order. especially,
If a socket-mounted DRAM module is used, it may not be possible to determine the set values in advance because it can be easily replaced. Therefore, we automatically checked the configuration of the installed DRAM module and found the DRAM module configuration.
Setting means for setting the configuration of the RAM module in a setting circuit h is provided. In other words, the DRAM is
By checking and setting the configuration of the module, it becomes possible to use the DRAM module without being aware of the configuration of the DRAM module to be installed.

A memory device equipped with this setting means will be described below as another embodiment. FIG. 7 is a configuration diagram showing another embodiment. The device shown in the figure is equipped with a setting means o,
This setting means o consists of a CPUp and a ROM (read only memory) q. CPUp is a higher-level controller that performs automatic setting processing, which will be described later.
02 is its address bus and data bus. Further, ROMq is a memory that stores a program for performing automatic setting processing. Note that the other configurations are the same as those of the embodiment shown in FIG. 1, so corresponding parts are given the same reference numerals and explanations thereof will be omitted.

Next, automatic setting processing for the memory device having the above configuration will be explained. 8, 9, and 10 are flowcharts for explaining the automatic setting process. First, D
Check whether the RAM module is installed. First, configure the DRAM module configuration to the minimum configuration (
In this example, it is set to 256KW x 8 bits) (
Step S1). That is, the setting value of the setting circuit h is d(b
1, b0) and e(b3, b2) are both "00". Next, the mounting status of DRAM modules d and e is set to unmounted (step S2), and then 0 to 3FFF
Write, read, and compare one location in the FH space (
Step S3). Here, if the check is OK (step S4), D
It is determined that the RAM module d is installed (step S5). If the check is not possible, the process proceeds to step S33, which will be described later, and the DRA set in step S1 is
The configuration values of M modules d and e are set in the setting circuit h.

Next, write/read/compare 40000H to 7FFFFH in the same manner as step S3 (step S6), and if this is OK (step S7),
Assuming that the DRAM module e is installed, install e=1 (step S8). If the check is not possible, the process proceeds to step S9 without setting installation e=1. In addition, here, if the configuration D is larger than the setting
Even if a RAM module is installed, there is no problem because the control unit outputs the inverted CAS signal only to each 256K byte space.

Next, the configuration of DRAM modules d and e is checked. First, the configuration of DRAM module d will be examined. The setting of DRAM module d is set to the second smallest configuration (1 MW×8 bits in this embodiment) (step S9). And 40000H+α (however, 0≦α≦
3FFFFH), specific data “A”
(however, 0≦A≦FFH) (step S1
0). After that, address α is read (step S11
), it is checked whether the data is "A" (step S12). Here, if the data is "A", it is determined that the installed module is not 1 MW x 8 bits but 256 KW x 8 bits (step S13). This is because if the configuration is 1MW x 8 bits, but it is 256KW x 8 bits,
The upper address is not given to the module and the inverted CA
Since only the S signal is given, addresses are accessed in duplicate in units of 256 KW. Therefore, if addresses are accessed in duplicate, it can be identified that a DRAM module with a configuration smaller than the setting is mounted. Furthermore, if data "A" cannot be read, since the addresses do not overlap, it can be seen that the installed module is 1 MW x 8 bits or 4 MW x 8 bits.

Next, the configuration is set to 4 MW x 8 bits (step S14), and 100,000 bits is set as in the above case.
Write specific data “B” to the address of H+β (0≦β≦FFFFFH) (however, 0≦B≦FFH)
) (Step S15). Then, the address β is read and it is checked whether the data is "B" (step S16). Here, if the data is "B" (step S17), the installed module is 4.
It is determined that it is not MW x 8 bits but 1 MW x 8 bits (step S18). The reason for this is that, as in the case described above, addresses appear to overlap in units of 1 MW. Furthermore, if data "B" cannot be read, it is found that the installed module is 4 MW x 8 bits (step S19).

After the identification of DRAM module d is completed, next, identification of DRAM module e is performed in the same manner. That is, it is checked whether the DRAM module e is installed (step S20), and if it is installed, the DRAM
The configuration of M module d is temporarily set to 256KW x 8 bits (step S21). In addition, if it is not implemented, the process moves to step S33 and the D
Setting values for the configuration of RAM modules d and e are set in the setting circuit h.

After that, the above-mentioned DRAM module d
As in the case of , the configuration of DRAM module e is set to 1MW.
×8 bits (step S22), address 80
Write data “A” to 000H+α (step S
23), reads address 40000H+α (step S24). If data "A" can be read (step S25), the configuration of DRAM module e is 256KW x 8 bits (step S26).
, if the read could not be performed, the configuration of the DRAM module e is set to 4 MW x 8 bits (step S27).
. After that, data “B” is placed at address 140000H+β.
” (step S28) and enter the address 4000.
0H+β is read (step S29). data"
If "B" is able to lead (step S30), the DRA
It is determined that the configuration of M module e is 1 MW x 8 bits (step S31), and if it cannot be read, 4
It is determined that the number is MW×8 bits (step S32). These reasons are the same as those mentioned above. After that,
The values of DRAM modules d and e obtained in the above operation are set in the setting circuit h (step S33), and the automatic search and setting operation is ended.

In each of the above embodiments, in order to avoid complication of explanation, two DRAM modules are used, and the configuration is
Although three types of 8-bit word configurations are used, word configurations other than these can also be handled in the same manner by the above method (however, the bit configurations are assumed to be the same). Furthermore, although an example in which a DRAM module is used as a storage module has been explained,
For example, SRAM and R
Even with other storage modules such as OM or magnetic disks, the same effects as in the above embodiment can be achieved as long as the module to be mounted is a convertible storage module.

[0028]

As explained above, according to the memory device of the present invention, the number of words of the memory modules to be mounted is set in advance in the setting circuit, and the mounted physical memory space of each memory module is determined based on this set value. Since the memory addresses of each storage module are controlled so that they are continuous, an economical and efficient memory device can be obtained. Also,
In a system in which the number of words of the memory module to be mounted is checked and the obtained number of words is set in the setting circuit, each memory module can be used without being aware of the number of words of the memory module to be mounted. It has the effect of being able to.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a memory device of the present invention.

FIG. 2 is an explanatory diagram showing register setting values in the memory device of the present invention.

FIG. 3 is an internal configuration diagram of a control circuit in the memory device of the present invention.

FIG. 4 is a diagram showing the timing of the memory device of the present invention.

FIG. 5 is a diagram showing truth values of a decoding control section in the memory device of the present invention.

FIG. 6 is an explanatory diagram of an example of a memory configuration of a memory device.

FIG. 7 is a configuration diagram of another embodiment of the memory device of the present invention.

FIG. 8 is a flowchart of another embodiment of the memory device of the present invention.

FIG. 9 is a flowchart of another embodiment of the memory device of the present invention.

FIG. 10 is a flowchart of another embodiment of the memory device of the present invention.

FIG. 11 is an explanatory diagram of typical types of DRAM modules.

FIG. 12 is a configuration diagram of a conventional memory device.

FIG. 13 is a diagram showing timing of a conventional memory device.

FIG. 14 is an explanatory diagram of an example of discontinuity of physical memory space of a conventional memory device.

[Explanation of symbols] d, e Memory module g Control circuit h Setting circuit o Setting means

Claims (2)

[Claims] 1. A memory device using a plurality of storage modules, comprising: a setting circuit that holds a setting value for the number of words that can be stored in each installed storage module, and a setting value based on the setting value held by the setting circuit. A memory device comprising: a control circuit that controls memory addresses of each of the storage modules so that a physical memory space in which the plurality of storage modules are mounted is continuous. 2. The device according to claim 1, further comprising a setting means for checking the number of words that can be stored in each memory module to be installed and setting the obtained number of words for each memory module in a setting circuit. memory device.