JPS59114657A - Memory interface circuit of microcomputer - Google Patents

Abstract

PURPOSE:To process the information of a large capacity in a short time by using a specific address signal as a chip selection signal of a memory and using an external counter for addresses of the memory. CONSTITUTION:A memory system 241 consists of a counter clock generating circuit 31, a counter 32 and a memory 33. The selection signals produced by a memory address decoder 22 are supplied to the circuit 31 and memory 33 of the system 241. The memory 33 uses the selection signal as a chip selection signal CS and then transfers data with a microprocessor 21 by means of the address signal of the counter 32, the selection signal of the decoder 22 and the RD and WR signals of the processor 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an interface circuit provided between a microprocessor and a memory in a microcomputer.

[Technical background of the invention]

The maximum memory space of a conventional 8-bit microprocessor is 64 bytes, and a method for using memory capacity greater than 64 bytes is bank switching.

FIG. 1 shows an example of memory space allocation when bank switching is used. In this figure, the memory spaces switched by bank switching are banks f2 and f3, and the signals necessary for this switching are supplied from the I10 circuit. When banks f1 and f2 are accessible areas,
Bank f3 is an inaccessible area, and bank 12
．． Data transfer between bank 13 uses the memory space of bank 11 to temporarily store data, generates a bank switching signal in I10 circuit using the output command of the microprocessor, and switches between bank 12 and bank f3. The method used is to move the data to the memory space of the destination bank. However, this method has the disadvantage that the execution time of the output command for the bank switching signal becomes long when the transferred data is large.

Further, since bank switching uses the microcomputer's OUT command, the number of banks that can be switched is limited, and there is a limit to the usable memory capacity.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory interface circuit for a microcomputer that can have a memory of virtually unlimited capacity and can process a large amount of information in a short time.

[Summary of the invention]

The Inter7Ace circuit according to the present invention uses a specific address signal from a microprocessor as a memory chip select signal, and uses an external counter to determine the memory address. Its basic feature is to make it happen.

In this case, a specific address signal and a control signal for determining its timing are used to generate a lock signal for the counter C2, thereby shortening the memory access time. Furthermore, a circuit for controlling commands (two units and counters) from a microprocessor is provided to enable access between arbitrary addresses 9 in the memory.

〔Effect of the invention〕

According to this invention, it is possible to process large amounts of information that was previously considered impossible with a microcomputer, and when performing arithmetic processing and data transfer on large amounts of data, conventional bank switching is no longer required. It becomes possible to transfer the used items at high speed.

[Embodiments of the invention]

FIG. 2 is a block diagram showing the configuration of a memory interface circuit of an 8-pit microcomputer according to an embodiment of the present invention.

The 8-bit microprocessor 21 has functions such as a single board microcomputer, and includes a CPU, memory, various interface circuits, etc. inside the system.

The memory address decoder 22 is the microprocessor 2
1 A.

~fi11 address signals and control signals for timing them, the memory systems 241.24.・
..., 24n chip select signal is generated.

FIG. 3 shows the configuration of the main parts of FIG. 2 in more detail.

The memory system 24□ in FIG. 2 is composed of a counter clock generation circuit 31, a counter 32, and a memory 33.

The select signal generated by the memory address decoder 22 is input to the counter clock generation circuit 31 and the memory 33 in the memory system 241. The memory 33 uses this signal as the chip select signal O8.

The counter clock generation circuit 34 uses this signal and the control signal of the microprocessor 21 to perform the counter 320 output count operation and the load operation for setting the data on D0 to D of data bus I)B to the counter value. making rock. These count operations, load operations,
The reset operation to set all the counter values to 60'' is controlled by the microprocessor 21 using the counter control signal generation circuit 23.

The memory 33 receives and receives data from the microprocessor 21 using the address signal of the counter 32 outputted by the above-mentioned control, the select signal of the memory address decoder 22, and the RD and WR signals of the microprocessor 21. I do.

For example, FIG. 4 shows the timing of a system using two (8085) CPUs (microprocessors).

Reference numeral 41 in the figure is a timing diagram showing the loading operation of the counter 32 in FIG.
The data of D is written. 42 is memory 3 in Figure 3.
3 is a timing diagram showing the writing and reading of data in memory 33 and 8-pit microphone a7°ot;, g-
21, the counter OK goes up after the data transfer is completed, and the value of the counter 32 automatically changes to 1.
I'm trying to move forward. Therefore, the time for generating the counter OK can be accommodated within the access time with the memory, so that when accessing continuously, the access can be made at the same speed as the access time of the internal memory of the microprocessor 21.

Further, the memory 33 shown in FIG. 3 can be easily increased in capacity by using a conventional memory interface. FIG. 5 is an example.

An address signal output from the counter 32 in FIG. 3 is input to the terminal 51. The lower address of this address is memory 55. ．． 55. . Since this upper address for chip selection can be increased by the counter 32 shown in FIG. 3, the capacity can be easily increased. The terminal 52 has a second
The RD and WR multiplied signals of the microprocessor 21 shown in the figure are inputted, and data is received and passed through the data bus DB of the terminal 53.

Next, the configuration and operation of FIG. 2 will be explained based on the above.

Memory system 241. . . 24n is different from the memory system 24. . . 24n shown in FIG. 3, except that the select signal output from the memory address decoder 22 is different. It has exactly the same configuration. Therefore, a specific large amount of information is stored in the memory system 241, and this information is sequentially retrieved and subjected to arithmetic processing, and the memory system 24. Let's consider data transfer, such as moving the results to . As mentioned above, the conventional system requires time for bank switching, but this system does not require that time, and also requires time from the microprocessor 21 to read and write to the memory. Since only two specific address signals of the address signals of ~A are required, the program itself is simple and the execution time is shortened.

Furthermore, by increasing the capacity of the memory system and using multiple memory systems, this system can have a memory capacity that was not possible with conventional systems.

FIG. 6 ν/Mako shows the structure of another embodiment of the invention. In this figure, the difference from the previous embodiment is that the counter clock generation circuit 3 in FIG. ....

In contrast, in Fig. 5, in order to reduce the circuit scale, the counter 62 (- the necessary clock part) is generated outside the memory system 641*642t e64n. is extracted by the clock extraction circuit 61.

To the address signal, the upper addresses of 〇 to A□ are input to the address decoder control circuit 65, and the lower addresses are input to the address decoder 66. Using the signals generated by the address decoder control circuit 65, the address decoder 66 is input to the memory system. 641.64. ,...64
n select signals are generated. A signal output from the address decoder control circuit 65 is input to a counter clock generation circuit 67, and a counter clock is output. This clock is the memory system 64
．． ．． 64. ,...

A clock extracting 9 circuit 61 in the clock extracting circuit 64n extracts a lock portion necessary for the counter 62 in response to a select signal inputted from the address decoder 66.

[Brief explanation of drawings]

FIG. 1 is a diagram showing allocation between memory walls using conventional bank replacement, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. Main parts are shown in detail (Figure 2, Figure 4 is a Tanoy-Mink diagram showing the operation of the same embodiment, Figure 5 is a diagram showing the internal structure of the memory in Figure 3,
FIG. 6 is a diagram showing the configuration of another embodiment of the invention. 21... 8-bit microprocessor, 22... address decoder for memory, 23... cylinder control signal generation circuit for counter, 24□-24n, 641-64n.
...Memory system, 31.61...Counter clock generation circuit, 32.62...Counter, 33.63
···memory. Applicant's agent Patent attorney Takehiko Suzue Figure 1 1

Claims (1)

[Claims] An interface circuit provided between a microcomputer processor and memory in a microcomputer,
means for selecting a memory chip using a specific address signal from a microprocessor; and means for giving a memory address using a counter. An in!'-7 eighth circuit for a memory of a microcomputer, characterized in that it is equipped with means for generating a control signal using a control signal for taking a command from a microprocessor, and means for controlling a command from a microprocessor (second counter).